Thomas Harte 5119997122 Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.		2017-05-30 22:41:23 -04:00
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C1540Bridge.h	Quick on-disk tidy up.	2016-07-09 15:44:55 -04:00
C1540Bridge.mm	Started trying to clean up, including commuting the C1540 source file name to match its class name but mainly by adding documentation.	2016-07-10 07:46:20 -04:00
Clock SignalTests-Bridging-Header.h	Adjusted slightly to adapt to latest Swift warnings.	2017-05-17 07:49:48 -04:00
DigitalPhaseLockedLoopBridge.h	Added test of perfect DPLL input timing.	2016-07-12 21:42:23 -04:00
DigitalPhaseLockedLoopBridge.mm	Added test of perfect DPLL input timing.	2016-07-12 21:42:23 -04:00
MOS6522Bridge.h	Quick on-disk tidy up.	2016-07-09 15:44:55 -04:00
MOS6522Bridge.mm	Quick on-disk tidy up.	2016-07-09 15:44:55 -04:00
MOS6532Bridge.h	Quick on-disk tidy up.	2016-07-09 15:44:55 -04:00
MOS6532Bridge.mm	Quick on-disk tidy up.	2016-07-09 15:44:55 -04:00
TestMachine6502.h	Renamed TestMachine to TestMachine6502 since there's going to be multiple of them.	2017-05-15 08:18:57 -04:00
TestMachine6502.mm	Added enough of a Z80 test machine to bridge up into Swift.	2017-05-16 22:05:42 -04:00
TestMachineZ80.h	Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.	2017-05-29 15:57:27 -04:00
TestMachineZ80.mm	Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.	2017-05-30 22:41:23 -04:00