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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-30 04:50:08 +00:00
CLK/OSBindings/Mac/Clock SignalTests
2016-07-28 11:32:14 -04:00
..
Bridges Added test of perfect DPLL input timing. 2016-07-12 21:42:23 -04:00
Wolfgang Lorenz 6502 test suite
6502_functional_test.bin
6502InterruptTests.swift
6502TimingTests.swift
6522Tests.swift
6532Tests.swift
AllSuiteA.bin
AllSuiteATests.swift
C1540Tests.swift Was transmitting bit levels backwards (probably?); 1540 now acknowledges byte received. 2016-07-09 18:06:49 -04:00
DPLLTests.swift Switched to a much-more straightforward PLL. I think I'm just fiddling now rather than moving forwards. Probably time to move on? 2016-07-28 11:32:14 -04:00
Info.plist
KlausDormannTests.swift
WolfgangLorenzTests.swift