Thomas Harte 6c09abc6cb Makes a flawed attempt to reformulate this exactly as two separate processes on a common clock with an interchange buffer. ... Specifically because closer inspection of the TMS modes shows it isn't quite valid to model output of one line as having fully completed prior to fetching of the next. So some sort of extra buffer is required. At which point it is most natural to continue with the logic that each fetch routine is oriented around the fetching process for a single line, and each output routine has the same view, suggesting separate read/write addresses. Something is wrong though, as video data is being output too rapidly (I think) and with occasional sync issues (again: subject to investigation).		2018-10-14 16:23:45 -04:00
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Implementation	Makes a flawed attempt to reformulate this exactly as two separate processes on a common clock with an interchange buffer.	2018-10-14 16:23:45 -04:00
9918.cpp	Makes a flawed attempt to reformulate this exactly as two separate processes on a common clock with an interchange buffer.	2018-10-14 16:23:45 -04:00
9918.hpp	Introduces horizontal counter latching and reading.	2018-10-11 19:56:32 -04:00