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130 lines
3.9 KiB
C++
130 lines
3.9 KiB
C++
//
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// Executor.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 29/04/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_M68k_Executor_hpp
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#define InstructionSets_M68k_Executor_hpp
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#include "Decoder.hpp"
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#include "Instruction.hpp"
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#include "Model.hpp"
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#include "Perform.hpp"
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#include "Status.hpp"
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namespace InstructionSet {
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namespace M68k {
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/// Maps the 68k function codes such that bits 0, 1 and 2 represent
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/// FC0, FC1 and FC2 respectively.
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enum class FunctionCode {
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UserData = 0b001,
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UserProgram = 0b010,
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SupervisorData = 0b101,
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SupervisorProgram = 0b110,
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InterruptAcknowledge = 0b111,
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};
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struct BusHandler {
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template <typename IntT> void write(uint32_t address, IntT value, FunctionCode function);
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template <typename IntT> IntT read(uint32_t address, FunctionCode function);
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};
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/// Ties together the decoder, sequencer and performer to provide an executor for 680x0 instruction streams.
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/// As is standard for these executors, no bus- or cache-level fidelity to any real 680x0 is attempted. This is
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/// simply an executor of 680x0 code.
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template <Model model, typename BusHandler> class Executor {
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public:
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Executor(BusHandler &);
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/// Executes the number of instructions specified;
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/// other events — such as initial reset or branching
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/// to exceptions — may be zero costed, and interrupts
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/// will not necessarily take effect immediately when signalled.
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void run_for_instructions(int);
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// Flow control.
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void consume_cycles(int) {}
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template <bool use_current_instruction_pc = true> void raise_exception(int);
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void did_update_status();
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template <typename IntT> void did_mulu(IntT) {}
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template <typename IntT> void did_muls(IntT) {}
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template <typename IntT> void complete_bcc(bool matched_condition, IntT offset);
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void complete_dbcc(bool matched_condition, bool overflowed, int16_t offset);
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void bsr(uint32_t offset);
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void jmp(uint32_t);
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void jsr(uint32_t offset);
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void rtr();
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void rts();
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void rte();
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void stop();
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void link(Preinstruction instruction, uint32_t offset);
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void unlink(uint32_t &address);
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void pea(uint32_t address);
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template <typename IntT> void movep(Preinstruction instruction, uint32_t source, uint32_t dest);
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template <typename IntT> void movem_toM(Preinstruction instruction, uint32_t source, uint32_t dest);
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template <typename IntT> void movem_toR(Preinstruction instruction, uint32_t source, uint32_t dest);
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void tas(Preinstruction instruction, uint32_t address);
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// TODO: ownership of this shouldn't be here.
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struct Registers {
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uint32_t data[8], address[7];
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uint32_t user_stack_pointer;
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uint32_t supervisor_stack_pointer;
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uint16_t status;
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uint32_t program_counter;
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};
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Registers get_state();
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void set_state(const Registers &);
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private:
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BusHandler &bus_handler_;
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Predecoder<model> decoder_;
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void reset();
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struct EffectiveAddress {
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CPU::SlicedInt32 value;
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bool requires_fetch;
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};
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EffectiveAddress calculate_effective_address(Preinstruction instruction, uint16_t opcode, int index);
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void read(DataSize size, uint32_t address, CPU::SlicedInt32 &value);
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void write(DataSize size, uint32_t address, CPU::SlicedInt32 value);
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template <typename IntT> IntT read(uint32_t address, bool is_from_pc = false);
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template <typename IntT> void write(uint32_t address, IntT value);
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template <typename IntT> IntT read_pc();
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uint32_t index_8bitdisplacement();
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// Processor state.
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Status status_;
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CPU::SlicedInt32 program_counter_;
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CPU::SlicedInt32 registers_[16]; // D0–D8, followed by A0–A8.
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CPU::SlicedInt32 stack_pointers_[2];
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uint32_t instruction_address_;
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int active_stack_pointer_ = 0;
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// A lookup table to ensure that A7 is adjusted by 2 rather than 1 in
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// postincrement and predecrement mode.
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static constexpr uint32_t byte_increments[] = {
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1, 1, 1, 1, 1, 1, 1, 2
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};
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};
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}
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}
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#include "Implementation/ExecutorImplementation.hpp"
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#endif /* InstructionSets_M68k_Executor_hpp */
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