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312 lines
9.0 KiB
C++
312 lines
9.0 KiB
C++
//
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// AtariST.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 03/10/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#include "AtariST.hpp"
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#include "../CRTMachine.hpp"
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#include "../../Processors/68000/68000.hpp"
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#include "../../Components/AY38910/AY38910.hpp"
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#include "../../Components/68901/MFP68901.hpp"
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#include "Video.hpp"
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#include "../../ClockReceiver/JustInTime.hpp"
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#include "../../ClockReceiver/ForceInline.hpp"
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#include "../../Outputs/Speaker/Implementation/LowpassSpeaker.hpp"
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#include "../Utility/MemoryPacker.hpp"
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#include "../Utility/MemoryFuzzer.hpp"
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namespace Atari {
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namespace ST {
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const int CLOCK_RATE = 8000000;
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using Target = Analyser::Static::Target;
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class ConcreteMachine:
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public Atari::ST::Machine,
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public CPU::MC68000::BusHandler,
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public CRTMachine::Machine {
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public:
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ConcreteMachine(const Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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mc68000_(*this),
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ay_(audio_queue_),
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speaker_(ay_) {
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set_clock_rate(CLOCK_RATE);
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speaker_.set_input_rate(CLOCK_RATE / 4);
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ram_.resize(512 * 512);
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Memory::Fuzz(ram_);
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std::vector<ROMMachine::ROM> rom_descriptions = {
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{"AtariST", "the TOS ROM", "tos100.img", 192*1024, 0x1a586c64}
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};
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const auto roms = rom_fetcher(rom_descriptions);
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if(!roms[0]) {
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throw ROMMachine::Error::MissingROMs;
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}
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Memory::PackBigEndian16(*roms[0], rom_);
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// Set up basic memory map.
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memory_map_[0] = BusDevice::MostlyRAM;
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for(int c = 1; c < 0xf0; ++c) memory_map_[c] = BusDevice::RAM;
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// This is appropriate for: TOS 1.x, no cartridge.
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for(int c = 0xf0; c < 0xfc; ++c) memory_map_[c] = BusDevice::Unassigned;
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for(int c = 0xfc; c < 0xff; ++c) memory_map_[c] = BusDevice::ROM;
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memory_map_[0xfa] = memory_map_[0xfb] = BusDevice::Cartridge;
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memory_map_[0xff] = BusDevice::IO;
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}
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~ConcreteMachine() {
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audio_queue_.flush();
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}
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// MARK: CRTMachine::Machine
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void set_scan_target(Outputs::Display::ScanTarget *scan_target) final {
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video_->set_scan_target(scan_target);
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}
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Outputs::Speaker::Speaker *get_speaker() final {
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return &speaker_;
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}
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void run_for(const Cycles cycles) final {
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mc68000_.run_for(cycles);
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}
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// MARK: MC68000::BusHandler
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using Microcycle = CPU::MC68000::Microcycle;
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HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int is_supervisor) {
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// Advance time.
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advance_time(cycle.length);
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// A null cycle leaves nothing else to do.
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if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
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/* TODO: DTack, bus error, VPA. */
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auto address = cycle.word_address();
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// if(cycle.data_select_active()) printf("%c %06x\n", (cycle.operation & Microcycle::Read) ? 'r' : 'w', *cycle.address & 0xffffff);
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uint16_t *memory;
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switch(memory_map_[address >> 15]) {
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case BusDevice::MostlyRAM:
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if(address < 4) {
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memory = rom_.data();
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break;
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}
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case BusDevice::RAM:
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memory = ram_.data();
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address &= ram_.size() - 1;
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// TODO: align with the next access window.
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break;
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case BusDevice::ROM:
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memory = rom_.data();
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address %= rom_.size();
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break;
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case BusDevice::Cartridge:
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/*
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TOS 1.0 appears to attempt to read from the catridge before it has setup
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the bus error vector. Therefore I assume no bus error flows.
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*/
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
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default: break;
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case Microcycle::SelectWord | Microcycle::Read:
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*cycle.value = 0xffff;
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = 0xff;
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break;
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}
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return HalfCycles(0);
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case BusDevice::Unassigned:
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assert(false);
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return HalfCycles(0);
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case BusDevice::IO:
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switch(address) {
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default:
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assert(false);
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case 0x7fc000:
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/* Memory controller configuration:
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b0, b1: bank 1
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b2, b3: bank 0
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00 = 128k
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01 = 512k
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10 = 2mb
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11 = reserved
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*/
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break;
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case 0x7fc400: /* PSG: write to select register, read to read register. */
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case 0x7fc401: /* PSG: write to write register. */
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if(!cycle.data_select_active()) return HalfCycles(0);
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// TODO: byte accesses to the odd addresses shouldn't obey logic below.
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advance_time(HalfCycles(2));
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update_audio();
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if(cycle.operation & Microcycle::Read) {
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ay_.set_control_lines(GI::AY38910::ControlLines(GI::AY38910::BC2 | GI::AY38910::BC1));
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cycle.value->halves.low = ay_.get_data_output();
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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} else {
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if(address == 0x7fc400) {
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ay_.set_control_lines(GI::AY38910::BC1);
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ay_.set_data_input(cycle.value->halves.low);
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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} else {
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ay_.set_control_lines(GI::AY38910::ControlLines(GI::AY38910::BC2 | GI::AY38910::BDIR));
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ay_.set_data_input(cycle.value->halves.low);
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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}
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}
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/*
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TODO: Port A:
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b7: reserved
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b6: "freely usable output (monitor jack)"
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b5: centronics strobe
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b4: RS-232 DTR output
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b3: RS-232 RTS output
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b2: select floppy drive 1
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b1: select floppy drive 0
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b0: "page choice signal for double-sided floppy drive"
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*/
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return HalfCycles(2);
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// The MFP block:
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case 0x7ffd00: case 0x7ffd01: case 0x7ffd02: case 0x7ffd03:
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case 0x7ffd04: case 0x7ffd05: case 0x7ffd06: case 0x7ffd07:
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case 0x7ffd08: case 0x7ffd09: case 0x7ffd0a: case 0x7ffd0b:
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case 0x7ffd0c: case 0x7ffd0d: case 0x7ffd0e: case 0x7ffd0f:
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case 0x7ffd10: case 0x7ffd11: case 0x7ffd12: case 0x7ffd13:
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case 0x7ffd14: case 0x7ffd15: case 0x7ffd16: case 0x7ffd17:
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case 0x7ffd18: case 0x7ffd19: case 0x7ffd1a: case 0x7ffd1b:
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case 0x7ffd1c: case 0x7ffd1d: case 0x7ffd1e: case 0x7ffd1f:
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if(!cycle.data_select_active()) return HalfCycles(0);
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// The lower data lines aren't connected.
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if(!cycle.upper_data_select()) {
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = 0xff;
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}
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return HalfCycles(0);
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}
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if(cycle.operation & Microcycle::Read) {
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const uint8_t value = mfp_->read(int(address));
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if(cycle.operation & Microcycle::SelectByte) {
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cycle.value->halves.low = value;
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} else {
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cycle.value->halves.high = value;
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cycle.value->halves.low = 0xff;
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}
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} else {
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if(cycle.operation & Microcycle::SelectByte) {
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mfp_->write(int(address), cycle.value->halves.low);
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} else {
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mfp_->write(int(address), cycle.value->halves.high);
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}
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}
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/*
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Atari ST GPIP bits:
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GPIP 7: monochrome monitor detect
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GPIP 6: RS-232 ring indicator
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GPIP 5: FD/HD interrupt
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GPIP 4: keyboard/MIDI interrupt
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GPIP 3: unused
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GPIP 2: RS-232 clear to send
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GPIP 1: RS-232 carrier detect
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GPIP 0: centronics busy
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*/
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break;
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}
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return HalfCycles(0);
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}
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// If control has fallen through to here, the access is either a read from ROM, or a read or write to RAM.
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
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default:
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break;
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = memory[address];
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = uint8_t(memory[address] >> cycle.byte_shift());
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break;
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case Microcycle::SelectWord:
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memory[address] = cycle.value->full;
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break;
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case Microcycle::SelectByte:
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memory[address] = uint16_t(
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(cycle.value->halves.low << cycle.byte_shift()) |
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(memory[address] & cycle.untouched_byte_mask())
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);
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break;
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}
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return HalfCycles(0);
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}
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void flush() {
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audio_queue_.perform();
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video_.flush();
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}
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private:
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forceinline void advance_time(HalfCycles length) {
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video_ += length;
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cycles_since_audio_update_ += length;
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mfp_ += length;
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}
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void update_audio() {
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speaker_.run_for(audio_queue_, cycles_since_audio_update_.divide_cycles(Cycles(4)));
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}
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CPU::MC68000::Processor<ConcreteMachine, true> mc68000_;
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JustInTimeActor<Video, HalfCycles> video_;
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JustInTimeActor<Motorola::MFP68901::MFP68901, HalfCycles> mfp_;
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Concurrency::DeferringAsyncTaskQueue audio_queue_;
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GI::AY38910::AY38910 ay_;
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Outputs::Speaker::LowpassSpeaker<GI::AY38910::AY38910> speaker_;
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HalfCycles cycles_since_audio_update_;
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std::vector<uint16_t> ram_;
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std::vector<uint16_t> rom_;
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enum class BusDevice {
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MostlyRAM, RAM, ROM, Cartridge, IO, Unassigned
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};
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BusDevice memory_map_[256];
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};
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}
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}
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using namespace Atari::ST;
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Machine *Machine::AtariST(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
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return new ConcreteMachine(*target, rom_fetcher);
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}
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Machine::~Machine() {}
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