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407 lines
12 KiB
C++
407 lines
12 KiB
C++
//
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// IWM.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 05/05/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#include "IWM.hpp"
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#include "../../Outputs/Log.hpp"
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using namespace Apple;
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namespace {
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constexpr int CA0 = 1 << 0;
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constexpr int CA1 = 1 << 1;
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constexpr int CA2 = 1 << 2;
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constexpr int LSTRB = 1 << 3;
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constexpr int ENABLE = 1 << 4;
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constexpr int DRIVESEL = 1 << 5; /* This means drive select, like on the original Disk II. */
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constexpr int Q6 = 1 << 6;
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constexpr int Q7 = 1 << 7;
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constexpr int SEL = 1 << 8; /* This is an additional input, not available on a Disk II, with a confusingly-similar name to SELECT but a distinct purpose. */
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}
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IWM::IWM(int clock_rate) :
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clock_rate_(clock_rate) {}
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// MARK: - Bus accessors
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uint8_t IWM::read(int address) {
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access(address);
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// Per Inside Macintosh:
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//
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// "Before you can read from any of the disk registers you must set up the state of the IWM so that it
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// can pass the data through to the MC68000's address space where you'll be able to read it. To do that,
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// you must first turn off Q7 by reading or writing dBase+q7L. Then turn on Q6 by accessing dBase+q6H.
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// After that, the IWM will be able to pass data from the disk's RD/SENSE line through to you."
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//
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// My understanding:
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//
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// Q6 = 1, Q7 = 0 reads the status register. The meaning of the top 'SENSE' bit is then determined by
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// the CA0,1,2 and SEL switches as described in Inside Macintosh, summarised above as RD/SENSE.
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if(address&1) {
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return 0xff;
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}
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switch(state_ & (Q6 | Q7 | ENABLE)) {
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default:
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LOG("[IWM] Invalid read\n");
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return 0xff;
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// "Read all 1s".
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// printf("Reading all 1s\n");
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// return 0xff;
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case 0:
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case ENABLE: { /* Read data register. Zeroing afterwards is a guess. */
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const auto result = data_register_;
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if(data_register_ & 0x80) {
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// printf("\n\nIWM:%02x\n\n", data_register_);
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// printf(".");
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data_register_ = 0;
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}
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// LOG("Reading data register: " << PADHEX(2) << int(result));
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return result;
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}
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case Q6: case Q6|ENABLE: {
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/*
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[If A = 0], Read status register:
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bits 0-4: same as mode register.
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bit 5: 1 = either /ENBL1 or /ENBL2 is currently low.
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bit 6: 1 = MZ (reserved for future compatibility; should always be read as 0).
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bit 7: 1 = SENSE input high; 0 = SENSE input low.
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(/ENBL1 is low when the first drive's motor is on; /ENBL2 is low when the second drive's motor is on.
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If the 1-second timer is enabled, motors remain on for one second after being programmatically disabled.)
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*/
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return uint8_t(
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(mode_&0x1f) |
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((state_ & ENABLE) ? 0x20 : 0x00) |
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(sense() & 0x80)
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);
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} break;
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case Q7: case Q7|ENABLE:
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/*
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Read write-handshake register:
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bits 0-5: reserved for future use (currently read as 1).
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bit 6: 1 = write state (0 = underrun has occurred; 1 = no underrun so far).
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bit 7: 1 = write data buffer ready for data (1 = ready; 0 = busy).
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*/
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// LOG("Reading write handshake: " << PADHEX(2) << (0x3f | write_handshake_));
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return 0x3f | write_handshake_;
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}
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return 0xff;
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}
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void IWM::write(int address, uint8_t input) {
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access(address);
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switch(state_ & (Q6 | Q7 | ENABLE)) {
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default: break;
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case Q7|Q6:
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/*
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Write mode register:
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bit 0: 1 = latch mode (should be set in asynchronous mode).
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bit 1: 0 = synchronous handshake protocol; 1 = asynchronous.
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bit 2: 0 = 1-second on-board timer enable; 1 = timer disable.
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bit 3: 0 = slow mode; 1 = fast mode.
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bit 4: 0 = 7Mhz; 1 = 8Mhz (7 or 8 mHz clock descriptor).
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bit 5: 1 = test mode; 0 = normal operation.
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bit 6: 1 = MZ-reset.
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bit 7: reserved for future expansion.
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*/
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mode_ = input;
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switch(mode_ & 0x18) {
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case 0x00: bit_length_ = Cycles(24); break; // slow mode, 7Mhz
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case 0x08: bit_length_ = Cycles(12); break; // fast mode, 7Mhz
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case 0x10: bit_length_ = Cycles(32); break; // slow mode, 8Mhz
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case 0x18: bit_length_ = Cycles(16); break; // fast mode, 8Mhz
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}
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LOG("IWM mode is now " << PADHEX(2) << int(mode_));
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break;
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case Q7|Q6|ENABLE: // Write data register.
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next_output_ = input;
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write_handshake_ &= ~0x80;
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break;
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}
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}
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// MARK: - Switch access
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void IWM::access(int address) {
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// Keep a record of switch state; bits in state_
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// should correlate with the anonymous namespace constants
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// defined at the top of this file — CA0, CA1, etc.
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address &= 0xf;
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const auto mask = 1 << (address >> 1);
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const auto old_state = state_;
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if(address & 1) {
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state_ |= mask;
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} else {
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state_ &= ~mask;
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}
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// React appropriately to ENABLE and DRIVESEL changes, and changes into/out of write mode.
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if(old_state != state_) {
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push_drive_state();
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switch(mask) {
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default: break;
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case ENABLE:
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if(address & 1) {
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if(drives_[active_drive_]) drives_[active_drive_]->set_enabled(true);
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} else {
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// If the 1-second delay is enabled, set up a timer for that.
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if(!(mode_ & 4)) {
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cycles_until_disable_ = Cycles(clock_rate_);
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} else {
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if(drives_[active_drive_]) drives_[active_drive_]->set_enabled(false);
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}
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}
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break;
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case DRIVESEL: {
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const int new_drive = address & 1;
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if(new_drive != active_drive_) {
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if(drives_[active_drive_]) drives_[active_drive_]->set_enabled(false);
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active_drive_ = new_drive;
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if(drives_[active_drive_]) {
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drives_[active_drive_]->set_enabled(state_ & ENABLE || (cycles_until_disable_ > Cycles(0)));
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push_drive_state();
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}
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}
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} break;
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case Q6:
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case Q7:
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select_shift_mode();
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break;
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}
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}
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}
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void IWM::set_select(bool enabled) {
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// Store SEL as an extra state bit.
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if(enabled) state_ |= SEL;
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else state_ &= ~SEL;
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push_drive_state();
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}
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void IWM::push_drive_state() {
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if(drives_[active_drive_]) {
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const uint8_t drive_control_lines =
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((state_ & CA0) ? IWMDrive::CA0 : 0) |
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((state_ & CA1) ? IWMDrive::CA1 : 0) |
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((state_ & CA2) ? IWMDrive::CA2 : 0) |
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((state_ & SEL) ? IWMDrive::SEL : 0) |
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((state_ & LSTRB) ? IWMDrive::LSTRB : 0);
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drives_[active_drive_]->set_control_lines(drive_control_lines);
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}
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}
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// MARK: - Active logic
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void IWM::run_for(const Cycles cycles) {
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// Check for a timeout of the motor-off timer.
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if(cycles_until_disable_ > Cycles(0)) {
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cycles_until_disable_ -= cycles;
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if(cycles_until_disable_ <= Cycles(0)) {
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cycles_until_disable_ = Cycles(0);
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if(drives_[active_drive_])
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drives_[active_drive_]->set_enabled(false);
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}
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}
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// Activity otherwise depends on mode and motor state.
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auto integer_cycles = cycles.as_integral();
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switch(shift_mode_) {
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case ShiftMode::Reading: {
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// Per the IWM patent, column 7, around line 35 onwards: "The expected time
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// is widened by approximately one-half an interval before and after the
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// expected time since the data is not precisely spaced when read due to
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// variations in drive speed and other external factors". The error_margin
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// here implements the 'after' part of that contract.
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const auto error_margin = Cycles(bit_length_.as_integral() >> 1);
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if(drive_is_rotating_[active_drive_]) {
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while(integer_cycles--) {
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drives_[active_drive_]->run_for(Cycles(1));
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++cycles_since_shift_;
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if(cycles_since_shift_ == bit_length_ + error_margin) {
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propose_shift(0);
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}
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}
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} else {
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while(cycles_since_shift_ + integer_cycles >= bit_length_ + error_margin) {
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const auto run_length = bit_length_ + error_margin - cycles_since_shift_;
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integer_cycles -= run_length.as_integral();
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cycles_since_shift_ += run_length;
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propose_shift(0);
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}
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cycles_since_shift_ += Cycles(integer_cycles);
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}
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} break;
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case ShiftMode::Writing:
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if(drives_[active_drive_]->is_writing()) {
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while(cycles_since_shift_ + integer_cycles >= bit_length_) {
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const auto cycles_until_write = bit_length_ - cycles_since_shift_;
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drives_[active_drive_]->run_for(cycles_until_write);
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// Output a flux transition if the top bit is set.
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drives_[active_drive_]->write_bit(shift_register_ & 0x80);
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shift_register_ <<= 1;
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integer_cycles -= cycles_until_write.as_integral();
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cycles_since_shift_ = Cycles(0);
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--output_bits_remaining_;
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if(!output_bits_remaining_) {
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if(!(write_handshake_ & 0x80)) {
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write_handshake_ |= 0x80;
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shift_register_ = next_output_;
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output_bits_remaining_ = 8;
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// LOG("Next byte: " << PADHEX(2) << int(shift_register_));
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} else {
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write_handshake_ &= ~0x40;
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drives_[active_drive_]->end_writing();
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// printf("\n");
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LOG("Overrun; done.");
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select_shift_mode();
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}
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}
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}
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cycles_since_shift_ = integer_cycles;
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if(integer_cycles) {
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drives_[active_drive_]->run_for(cycles_since_shift_);
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}
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} else {
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drives_[active_drive_]->run_for(cycles);
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}
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break;
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case ShiftMode::CheckingWriteProtect:
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if(integer_cycles < 8) {
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shift_register_ = (shift_register_ >> integer_cycles) | (sense() & (0xff << (8 - integer_cycles)));
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} else {
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shift_register_ = sense();
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}
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/* Deliberate fallthrough. */
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default:
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if(drive_is_rotating_[active_drive_]) drives_[active_drive_]->run_for(cycles);
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break;
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}
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}
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void IWM::select_shift_mode() {
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// Don't allow an ongoing write to be interrupted.
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if(shift_mode_ == ShiftMode::Writing && drives_[active_drive_] && drives_[active_drive_]->is_writing()) return;
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const auto old_shift_mode = shift_mode_;
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switch(state_ & (Q6|Q7)) {
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default: shift_mode_ = ShiftMode::CheckingWriteProtect; break;
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case 0: shift_mode_ = ShiftMode::Reading; break;
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case Q7:
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// "The IWM is put into the write state by a transition from the write protect sense state to the
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// write load state".
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if(shift_mode_ == ShiftMode::CheckingWriteProtect) shift_mode_ = ShiftMode::Writing;
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break;
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}
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// If writing mode just began, set the drive into write mode and cue up the first output byte.
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if(drives_[active_drive_] && old_shift_mode != ShiftMode::Writing && shift_mode_ == ShiftMode::Writing) {
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drives_[active_drive_]->begin_writing(Storage::Time(1, clock_rate_ / bit_length_.as_integral()), false);
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shift_register_ = next_output_;
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write_handshake_ |= 0x80 | 0x40;
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output_bits_remaining_ = 8;
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LOG("Seeding output with " << PADHEX(2) << shift_register_);
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}
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}
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uint8_t IWM::sense() {
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return drives_[active_drive_] ? (drives_[active_drive_]->read() ? 0xff : 0x00) : 0xff;
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}
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void IWM::process_event(const Storage::Disk::Drive::Event &event) {
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if(shift_mode_ != ShiftMode::Reading) return;
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switch(event.type) {
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case Storage::Disk::Track::Event::IndexHole: return;
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case Storage::Disk::Track::Event::FluxTransition:
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propose_shift(1);
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break;
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}
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}
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void IWM::propose_shift(uint8_t bit) {
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// TODO: synchronous mode.
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// LOG("Shifting input");
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// See above for text from the IWM patent, column 7, around line 35 onwards.
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// The error_margin here implements the 'before' part of that contract.
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//
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// Basic effective logic: if at least 1 is fozund in the bit_length_ cycles centred
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// on the current expected bit delivery time as implied by cycles_since_shift_,
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// shift in a 1 and start a new window wherever the first found 1 was.
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//
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// If no 1s are found, shift in a 0 and don't alter expectations as to window placement.
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const auto error_margin = Cycles(bit_length_.as_integral() >> 1);
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if(bit && cycles_since_shift_ < error_margin) return;
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shift_register_ = uint8_t((shift_register_ << 1) | bit);
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if(shift_register_ & 0x80) {
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data_register_ = shift_register_;
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shift_register_ = 0;
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}
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if(bit)
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cycles_since_shift_ = Cycles(0);
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else
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cycles_since_shift_ -= bit_length_;
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}
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void IWM::set_drive(int slot, IWMDrive *drive) {
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drives_[slot] = drive;
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drive->set_event_delegate(this);
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drive->set_clocking_hint_observer(this);
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}
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void IWM::set_component_prefers_clocking(ClockingHint::Source *component, ClockingHint::Preference clocking) {
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const bool is_rotating = clocking != ClockingHint::Preference::None;
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if(component == static_cast<ClockingHint::Source *>(drives_[0])) {
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drive_is_rotating_[0] = is_rotating;
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} else {
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drive_is_rotating_[1] = is_rotating;
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}
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}
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void IWM::set_activity_observer(Activity::Observer *observer) {
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if(drives_[0]) drives_[0]->set_activity_observer(observer, "Internal Floppy", true);
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if(drives_[1]) drives_[1]->set_activity_observer(observer, "External Floppy", true);
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}
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