Thomas Harte 7af3de010e Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.

2017-08-23 22:25:31 -04:00

..

6502

Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.

2017-08-21 21:56:42 -04:00

Z80

Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.

2017-08-23 22:25:31 -04:00

AllRAMProcessor.cpp

Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.

2017-07-27 20:17:13 -04:00

AllRAMProcessor.hpp

Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.

2017-07-27 20:17:13 -04:00

RegisterSizes.hpp

Noodled around with initial state.

2017-05-29 19:25:08 -04:00