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534 lines
18 KiB
C++
534 lines
18 KiB
C++
//
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// MemoryMap.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 04/01/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#include "MemoryMap.hpp"
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using namespace Apple::IIgs;
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using PagingType = Apple::II::PagingType;
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void MemoryMap::set_storage(std::vector<uint8_t> &ram, std::vector<uint8_t> &rom) {
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// Keep a pointer for later; also note the proper RAM offset.
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ram_base_ = ram.data();
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shadow_base_[0] = ram_base_; // i.e. all unshadowed writes go to where they've already gone (to make a no-op).
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shadow_base_[1] = &ram[ram.size() - 0x02'0000]; // i.e. all shadowed writes go somewhere in the last
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// 128bk of RAM.
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// Establish bank mapping.
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uint8_t next_region = 0;
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auto region = [&]() -> uint8_t {
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assert(next_region != this->regions_.size());
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return next_region++;
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};
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auto set_region = [this](uint8_t bank, uint16_t start, uint16_t end, uint8_t region) {
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assert((end == 0xffff) || !(end&0xff));
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assert(!(start&0xff));
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// Fill in memory map.
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size_t target = size_t((bank << 8) | (start >> 8));
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for(int c = start; c < end; c += 0x100) {
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region_map_[target] = region;
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++target;
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}
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};
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auto set_regions = [set_region, region](uint8_t bank, std::initializer_list<uint16_t> addresses, std::vector<uint8_t> allocated_regions = {}) {
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uint16_t previous = 0x0000;
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auto next_region = allocated_regions.begin();
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for(uint16_t address: addresses) {
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set_region(bank, previous, address, next_region != allocated_regions.end() ? *next_region : region());
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previous = address;
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assert(next_region != allocated_regions.end() || allocated_regions.empty());
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if(next_region != allocated_regions.end()) ++next_region;
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}
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assert(next_region == allocated_regions.end());
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};
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// Current beliefs about the IIgs memory map:
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//
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// * language card banking applies to banks $00, $01, $e0 and $e1;
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// * auxiliary memory switches apply to bank $00 only;
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// * shadowing may be enabled only on banks $00 and $01, or on all RAM pages; and
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// * whether bit 16 of the address is passed to the Mega II is selectable — this affects both the destination
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// of odd-bank shadows, and whether bank $e1 is actually distinct from $e0.
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//
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// So:
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//
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// * bank $00 needs to be divided by auxiliary and language card zones;
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// * banks $01, $e0 and $e1 need to be divided by language card zones only; and
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// * ROM banks and all other fast RAM banks don't need subdivision.
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// Language card zones:
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//
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// $D000–$E000 4kb window, into either bank 1 or bank 2
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// $E000–end 12kb window, always the same RAM.
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// Auxiliary zones:
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//
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// $0000–$0200 Zero page (and stack)
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// $0200–$0400 [space in between]
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// $0400–$0800 Text Page 1
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// $0800–$2000 [space in between]
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// $2000–$4000 High-res Page 1
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// $4000–$C000 [space in between]
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// Card zones:
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//
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// $C100–$C2FF either cards or IIe-style ROM
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// $C300–$C3FF IIe-supplied 80-column card replacement ROM
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// $C400–$C7FF either cards or IIe-style ROM
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// $C800–$CFFF Standard extended card area
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// Reserve region 0 as that for unmapped memory.
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region();
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// Bank $00: all locations potentially affected by the auxiliary switches or the
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// language switches.
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set_regions(0x00, {
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0x0200, 0x0400, 0x0800,
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0x2000, 0x4000,
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0xc000, 0xc100, 0xc300, 0xc400, 0xc800,
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0xd000, 0xe000,
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0xffff
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});
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// Bank $01: all locations potentially affected by the language switches and card switches.
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set_regions(0x01, {
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0xc000, 0xc100, 0xc300, 0xc400, 0xc800,
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0xd000, 0xe000,
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0xffff
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});
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// Banks $02–[end of RAM]: a single region.
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const auto fast_region = region();
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const uint8_t fast_ram_bank_limit = uint8_t(ram.size() / 0x01'0000);
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for(uint8_t bank = 0x02; bank < fast_ram_bank_limit; bank++) {
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set_region(bank, 0x0000, 0xffff, fast_region);
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}
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// [Banks $80–$e0: empty].
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// Banks $e0, $e1: all locations potentially affected by the language switches or marked for IO.
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// Alas, separate regions are needed due to the same ROM appearing on both pages.
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for(uint8_t c = 0; c < 2; c++) {
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set_regions(0xe0 + c, {0xc000, 0xc100, 0xc300, 0xc400, 0xc800, 0xd000, 0xe000, 0xffff});
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}
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// [Banks $e2–[ROM start]: empty].
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// ROM banks: directly mapped to ROM.
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const uint8_t rom_bank_count = uint8_t(rom.size() >> 16);
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const uint8_t first_rom_bank = uint8_t(0x100 - rom_bank_count);
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const uint8_t rom_region = region();
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for(uint8_t c = 0; c < rom_bank_count; ++c) {
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set_region(first_rom_bank + c, 0x0000, 0xffff, rom_region);
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}
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// Apply proper storage to those banks.
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auto set_storage = [this](uint32_t address, const uint8_t *read, uint8_t *write) {
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// Don't allow the reserved null region to be modified.
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assert(region_map_[address >> 8]);
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// Either set or apply a quick bit of testing as to the logic at play.
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auto ®ion = regions_[region_map_[address >> 8]];
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if(read) read -= address;
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if(write) write -= address;
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if(!region.read) {
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region.read = read;
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region.write = write;
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} else {
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assert(region.read == read);
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assert(region.write == write);
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}
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};
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// This is highly redundant, but decouples this step from the above.
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for(size_t c = 0; c < 0x80'0000; c += 0x100) {
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if(c < ram.size() - 0x02'0000) {
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set_storage(uint32_t(c), &ram[c], &ram[c]);
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}
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}
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uint8_t *const slow_ram = &ram[ram.size() - 0x02'0000] - 0xe0'0000;
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for(size_t c = 0xe0'0000; c < 0xe2'0000; c += 0x100) {
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set_storage(uint32_t(c), &slow_ram[c], &slow_ram[c]);
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}
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for(uint32_t c = 0; c < uint32_t(rom_bank_count); c++) {
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set_storage((first_rom_bank + c) << 16, &rom[c << 16], nullptr);
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}
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// Set shadowing as working from banks 0 and 1 (forever).
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shadow_banks_[0] = true;
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// TODO: set 1Mhz flags.
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// Apply initial language/auxiliary state.
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set_paging<~0>();
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}
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void MemoryMap::set_shadow_register(uint8_t value) {
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const uint8_t diff = value ^ shadow_register_;
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shadow_register_ = value;
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if(diff & 0x40) { // IO/language-card inhibit.
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set_paging<PagingType::LanguageCard | PagingType::CardArea>();
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}
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if(diff & 0x3f) {
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set_shadowing();
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}
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}
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uint8_t MemoryMap::get_shadow_register() const {
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return shadow_register_;
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}
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void MemoryMap::set_speed_register(uint8_t value) {
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speed_register_ = value;
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// Enable or disable shadowing from banks 0x02–0x80.
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for(size_t c = 0x01; c < 0x40; c++) {
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shadow_banks_[c] = speed_register_ & 0x10;
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}
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}
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void MemoryMap::set_state_register(uint8_t value) {
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auxiliary_switches_.set_state(value);
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language_card_.set_state(value);
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}
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uint8_t MemoryMap::get_state_register() const {
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return language_card_.get_state() | auxiliary_switches_.get_state();
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}
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void MemoryMap::access(uint16_t address, bool is_read) {
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auxiliary_switches_.access(address, is_read);
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if((address & 0xfff0) == 0xc080) language_card_.access(address, is_read);
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}
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void MemoryMap::assert_is_region([[maybe_unused]] uint8_t start, [[maybe_unused]] uint8_t end) {
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assert(region_map_[start] == region_map_[start-1]+1);
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assert(region_map_[end-1] == region_map_[start]);
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assert(region_map_[end] == region_map_[end-1]+1);
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}
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template <int type> void MemoryMap::set_paging() {
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// Establish whether main or auxiliary RAM
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// is exposed in bank $00 for a bunch of regions.
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if constexpr (type & PagingType::Main) {
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const auto set = [&](std::size_t page, const auto &flags) {
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auto ®ion = regions_[region_map_[page]];
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region.read = flags.read ? &ram_base_[0x01'0000] : ram_base_;
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region.write = flags.write ? &ram_base_[0x01'0000] : ram_base_;
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};
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const auto state = auxiliary_switches_.main_state();
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// Base: $0200–$03FF.
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set(0x02, state.base);
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assert_is_region(0x02, 0x04);
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// Region $0400–$07ff.
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set(0x04, state.region_04_08);
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assert_is_region(0x04, 0x08);
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// Base: $0800–$1FFF.
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set(0x08, state.base);
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assert_is_region(0x08, 0x20);
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// Region $2000–$3FFF.
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set(0x20, state.region_20_40);
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assert_is_region(0x20, 0x40);
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// Base: $4000–$BFFF.
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set(0x40, state.base);
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assert_is_region(0x40, 0xc0);
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}
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// Update whether base or auxiliary RAM is visible in: (i) the zero
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// and stack pages; and (ii) anywhere that the language card is exposing RAM instead of ROM.
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if constexpr (bool(type & PagingType::ZeroPage)) {
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// Affects bank $00 only, and should be a single region.
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auto ®ion = regions_[region_map_[0]];
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region.read = region.write = auxiliary_switches_.zero_state() ? &ram_base_[0x01'0000] : ram_base_;
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assert(region_map_[0x0000] == region_map_[0x0001]);
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assert(region_map_[0x0001]+1 == region_map_[0x0002]);
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}
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// Establish whether ROM or card switches are exposed in the distinct
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// regions C100–C2FF, C300–C3FF, C400–C7FF and C800–CFFF.
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//
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// On the IIgs it intersects with the current shadow register.
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if constexpr (bool(type & (PagingType::CardArea | PagingType::Main))) {
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const bool inhibit_banks0001 = shadow_register_ & 0x40;
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const auto state = auxiliary_switches_.card_state();
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auto apply = [&state, this](uint32_t bank_base) {
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auto &c0_region = regions_[region_map_[bank_base | 0xc0]];
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auto &c1_region = regions_[region_map_[bank_base | 0xc1]];
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auto &c3_region = regions_[region_map_[bank_base | 0xc3]];
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auto &c4_region = regions_[region_map_[bank_base | 0xc4]];
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auto &c8_region = regions_[region_map_[bank_base | 0xc8]];
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const uint8_t *const rom = ®ions_[region_map_[0xffd0]].read[0xffc100] - ((bank_base << 8) + 0xc100);
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// This is applied dynamically as it may be added or lost in banks $00 and $01.
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c0_region.flags |= Region::IsIO;
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const auto apply_region = [&](bool flag, auto ®ion) {
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region.write = nullptr;
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if(flag) {
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region.read = rom;
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region.flags &= ~Region::IsIO;
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} else {
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region.flags |= Region::IsIO;
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}
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};
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apply_region(state.region_C1_C3, c1_region);
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apply_region(state.region_C3, c3_region);
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apply_region(state.region_C4_C8, c4_region);
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apply_region(state.region_C8_D0, c8_region);
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// Sanity checks.
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assert(region_map_[bank_base | 0xc1] == region_map_[bank_base | 0xc0]+1);
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assert(region_map_[bank_base | 0xc2] == region_map_[bank_base | 0xc1]);
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assert(region_map_[bank_base | 0xc3] == region_map_[bank_base | 0xc2]+1);
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assert(region_map_[bank_base | 0xc4] == region_map_[bank_base | 0xc3]+1);
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assert(region_map_[bank_base | 0xc7] == region_map_[bank_base | 0xc4]);
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assert(region_map_[bank_base | 0xc8] == region_map_[bank_base | 0xc7]+1);
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assert(region_map_[bank_base | 0xcf] == region_map_[bank_base | 0xc8]);
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assert(region_map_[bank_base | 0xd0] == region_map_[bank_base | 0xcf]+1);
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};
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if(inhibit_banks0001) {
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// Set no IO in the Cx00 range for banks $00 and $01, just
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// regular RAM (or possibly auxiliary).
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const auto auxiliary_state = auxiliary_switches_.main_state();
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for(uint8_t region = region_map_[0x00c0]; region < region_map_[0x00d0]; region++) {
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regions_[region].read = auxiliary_state.base.read ? &ram_base_[0x01'0000] : ram_base_;
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regions_[region].write = auxiliary_state.base.write ? &ram_base_[0x01'0000] : ram_base_;
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regions_[region].flags &= ~Region::IsIO;
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}
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for(uint8_t region = region_map_[0x01c0]; region < region_map_[0x01d0]; region++) {
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regions_[region].read = regions_[region].write = ram_base_;
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regions_[region].flags &= ~Region::IsIO;
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}
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} else {
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// Obey the card state for banks $00 and $01.
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apply(0x0000);
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apply(0x0100);
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}
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// Obey the card state for banks $e0 and $e1.
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apply(0xe000);
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apply(0xe100);
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}
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// Update the region from
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// $D000 onwards as per the state of the language card flags — there may
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// end up being ROM or RAM (or auxiliary RAM), and the first 4kb of it
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// may be drawn from either of two pools.
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if constexpr (bool(type & (PagingType::LanguageCard | PagingType::ZeroPage | PagingType::Main))) {
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const auto language_state = language_card_.state();
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const auto zero_state = auxiliary_switches_.zero_state();
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const auto main = auxiliary_switches_.main_state();
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const bool inhibit_banks0001 = shadow_register_ & 0x40;
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auto apply = [&language_state, this](uint32_t bank_base, uint8_t *ram) {
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// This assumes bank 1 is the one before bank 2 when RAM is linear.
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uint8_t *const d0_ram_bank = ram - (language_state.bank2 ? 0x0000 : 0x1000);
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// Crib the ROM pointer from a page it's always visible on.
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const uint8_t *const rom = ®ions_[region_map_[0xffd0]].read[0xff'd000] - ((bank_base << 8) + 0xd000);
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auto &d0_region = regions_[region_map_[bank_base | 0xd0]];
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d0_region.read = language_state.read ? d0_ram_bank : rom;
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d0_region.write = language_state.write ? nullptr : d0_ram_bank;
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auto &e0_region = regions_[region_map_[bank_base | 0xe0]];
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e0_region.read = language_state.read ? ram : rom;
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e0_region.write = language_state.write ? nullptr : ram;
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// Assert assumptions made above re: memory layout.
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assert(region_map_[bank_base | 0xd0] + 1 == region_map_[bank_base | 0xe0]);
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assert(region_map_[bank_base | 0xe0] == region_map_[bank_base | 0xff]);
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};
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auto set_no_card = [this](uint32_t bank_base, uint8_t *read, uint8_t *write) {
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auto &d0_region = regions_[region_map_[bank_base | 0xd0]];
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d0_region.read = read;
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d0_region.write = write;
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auto &e0_region = regions_[region_map_[bank_base | 0xe0]];
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e0_region.read = read;
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e0_region.write = write;
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// Assert assumptions made above re: memory layout.
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assert(region_map_[bank_base | 0xd0] + 1 == region_map_[bank_base | 0xe0]);
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assert(region_map_[bank_base | 0xe0] == region_map_[bank_base | 0xff]);
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};
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if(inhibit_banks0001) {
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set_no_card(0x0000,
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main.base.read ? &ram_base_[0x01'0000] : ram_base_,
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main.base.write ? &ram_base_[0x01'0000] : ram_base_);
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set_no_card(0x0100, ram_base_, ram_base_);
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} else {
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apply(0x0000, zero_state ? &ram_base_[0x01'0000] : ram_base_);
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apply(0x0100, ram_base_);
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}
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// The pointer stored in region_map_[0xe000] has already been adjusted for
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// the 0xe0'0000 addressing offset.
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uint8_t *const e0_ram = regions_[region_map_[0xe000]].write;
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apply(0xe000, e0_ram);
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apply(0xe100, e0_ram);
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}
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}
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// IIgs specific: sets or resets the ::IsShadowed flag across affected banks as
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// per the current state of the shadow register.
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//
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// Completely distinct from the auxiliary and language card switches.
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void MemoryMap::set_shadowing() {
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// Relevant bits:
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//
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// b5: inhibit shadowing, text page 2 [if ROM 03; as if always set otherwise]
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// b4: inhibit shadowing, auxiliary high-res graphics
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// b3: inhibit shadowing, super high-res graphics
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// b2: inhibit shadowing, high-res graphics page 2
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// b1: inhibit shadowing, high-res graphics page 1
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// b0: inhibit shadowing, text page 1
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//
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// The interpretations of how the overlapping high-res and super high-res inhibit
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// bits apply used below is taken from The Apple IIgs Technical Reference, P. 178.
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// Of course, zones are:
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//
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// $0400–$0800 Text Page 1
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// $0800–$0C00 Text Page 2 [ROM 03 machines]
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// $2000–$4000 High-res Page 1, and Super High-res in odd banks
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// $4000–$6000 High-res Page 2, and Huper High-res in odd banks
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// $6000–$a000 Odd banks only, rest of Super High-res
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// [plus IO and language card space, subject to your definition of shadowing]
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enum Inhibit {
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TextPage1 = 0x01,
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HighRes1 = 0x02,
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HighRes2 = 0x04,
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SuperHighRes = 0x08,
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AuxiliaryHighRes = 0x10,
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TextPage2 = 0x20,
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};
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// Clear all shadowing.
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shadow_pages_.reset();
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// Text Page 1, main and auxiliary — $0400–$0800.
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{
|
||
const bool should_shadow_text1 = !(shadow_register_ & Inhibit::TextPage1);
|
||
if(should_shadow_text1) {
|
||
shadow_pages_ |= shadow_text1_;
|
||
}
|
||
}
|
||
|
||
// Text Page 2, main and auxiliary — 0x0800–0x0c00.
|
||
//
|
||
// The mask applied will be all 0 for a pre-ROM03 machine.
|
||
{
|
||
const bool should_shadow_text2 = !(shadow_register_ & Inhibit::TextPage2);
|
||
if(should_shadow_text2) {
|
||
shadow_pages_ |= shadow_text2_;
|
||
}
|
||
}
|
||
|
||
// Hi-res graphics Page 1, main and auxiliary — $2000–$4000;
|
||
// also part of the super high-res graphics page on odd pages.
|
||
//
|
||
// Even test applied:
|
||
// high-res graphics page 1 inhibit bit alone is definitive.
|
||
//
|
||
// Odd test:
|
||
// (high-res graphics inhibit or auxiliary high res graphics inhibit) _and_
|
||
// (super high-res inhibit).
|
||
//
|
||
{
|
||
const bool should_shadow_highres1 = !(shadow_register_ & Inhibit::HighRes1);
|
||
if(should_shadow_highres1) {
|
||
shadow_pages_ |= shadow_highres1_;
|
||
}
|
||
|
||
const bool should_shadow_aux_highres1 = !(
|
||
shadow_register_ & (Inhibit::HighRes1 | Inhibit::AuxiliaryHighRes) &&
|
||
shadow_register_ & Inhibit::SuperHighRes
|
||
);
|
||
if(should_shadow_aux_highres1) {
|
||
shadow_pages_ |= shadow_highres1_aux_;
|
||
}
|
||
}
|
||
|
||
// Hi-res graphics Page 2, main and auxiliary — $4000–$6000;
|
||
// also part of the super high-res graphics page.
|
||
//
|
||
// Test applied: much like that for page 1.
|
||
{
|
||
const bool should_shadow_highres2 = !(shadow_register_ & Inhibit::HighRes2);
|
||
if(should_shadow_highres2) {
|
||
shadow_pages_ |= shadow_highres2_;
|
||
}
|
||
|
||
const bool should_shadow_aux_highres2 = !(
|
||
shadow_register_ & (Inhibit::HighRes2 | Inhibit::AuxiliaryHighRes) &&
|
||
shadow_register_ & Inhibit::SuperHighRes
|
||
);
|
||
if(should_shadow_aux_highres2) {
|
||
shadow_pages_ |= shadow_highres2_aux_;
|
||
}
|
||
}
|
||
|
||
// Residue of Super Hi-Res — $6000–$a000 (odd pages only).
|
||
//
|
||
// Test applied:
|
||
// auxiliary high res graphics inhibit and super high-res inhibit
|
||
{
|
||
const bool should_shadow_superhighres = !(
|
||
shadow_register_ & Inhibit::SuperHighRes &&
|
||
shadow_register_ & Inhibit::AuxiliaryHighRes
|
||
);
|
||
if(should_shadow_superhighres) {
|
||
shadow_pages_ |= shadow_superhighres_;
|
||
}
|
||
}
|
||
}
|
||
|
||
void MemoryMap::setup_shadow_maps(bool is_rom03) {
|
||
static constexpr int shadow_shift = 10;
|
||
static constexpr int auxiliary_offset = 0x1'0000 >> shadow_shift;
|
||
|
||
for(size_t c = 0x0400 >> shadow_shift; c < 0x0800 >> shadow_shift; c++) {
|
||
shadow_text1_[c] = shadow_text1_[c+auxiliary_offset] = true;
|
||
}
|
||
|
||
// Shadowing of text page 2 was added only with the ROM03 machine.
|
||
if(is_rom03) {
|
||
for(size_t c = 0x0800 >> shadow_shift; c < 0x0c00 >> shadow_shift; c++) {
|
||
shadow_text2_[c] = shadow_text2_[c+auxiliary_offset] = true;
|
||
}
|
||
}
|
||
|
||
for(size_t c = 0x2000 >> shadow_shift; c < 0x4000 >> shadow_shift; c++) {
|
||
shadow_highres1_[c] = true;
|
||
shadow_highres1_aux_[c+auxiliary_offset] = true;
|
||
}
|
||
|
||
for(size_t c = 0x4000 >> shadow_shift; c < 0x6000 >> shadow_shift; c++) {
|
||
shadow_highres2_[c] = true;
|
||
shadow_highres2_aux_[c+auxiliary_offset] = true;
|
||
}
|
||
|
||
for(size_t c = 0x6000 >> shadow_shift; c < 0xa000 >> shadow_shift; c++) {
|
||
shadow_superhighres_[c+auxiliary_offset] = true;
|
||
}
|
||
}
|