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391 lines
15 KiB
Plaintext
391 lines
15 KiB
Plaintext
//
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// PowerPCDecoderTests.m
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// Clock Signal
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//
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// Created by Thomas Harte on 02/01/2021.
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// Copyright 2021 Thomas Harte. All rights reserved.
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//
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#import <XCTest/XCTest.h>
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#include "../../../InstructionSets/PowerPC/Decoder.hpp"
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namespace {
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using Operation = InstructionSet::PowerPC::Operation;
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using Instruction = InstructionSet::PowerPC::Instruction;
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}
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@interface PowerPCDecoderTests : XCTestCase
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@end
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/*!
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Tests PowerPC decoding by throwing a bunch of randomly-generated
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word streams and checking that the result matches what I got from a
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disassembler elsewhere.
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*/
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@implementation PowerPCDecoderTests {
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Instruction instructions[32];
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}
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// MARK: - Specific instruction asserts.
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- (void)assertUndefined:(Instruction &)instruction {
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XCTAssertEqual(instruction.operation, Operation::Undefined);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation rD:(int)rD rA:(int)rA simm:(int)simm {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.rD(), rD);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.simm(), simm);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation rD:(int)rD rA:(int)rA d:(int)d {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.rD(), rD);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.d(), d);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation rA:(int)rA rS:(int)rS uimm:(int)uimm {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.rS(), rS);
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XCTAssertEqual(instruction.uimm(), uimm);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation rS:(int)rS rA:(int)rA d:(int)d {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.rS(), rS);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.d(), d);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation frD:(int)frD rA:(int)rA d:(int)d {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.frD(), frD);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.d(), d);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation frS:(int)frS rA:(int)rA d:(int)d {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.frS(), frS);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.d(), d);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation li:(uint32_t)li lk:(BOOL)lk aa:(BOOL)aa {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.li(), li);
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XCTAssertEqual(!!instruction.lk(), lk);
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XCTAssertEqual(!!instruction.aa(), aa);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation bo:(int)bo bi:(int)bi bd:(int)bd lk:(BOOL)lk aa:(BOOL)aa {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.bo(), bo);
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XCTAssertEqual(instruction.bi(), bi);
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XCTAssertEqual(instruction.bd(), bd);
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XCTAssertEqual(!!instruction.lk(), lk);
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XCTAssertEqual(!!instruction.aa(), aa);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation rA:(int)rA rS:(int)rS rB:(int)rB mb:(int)mb me:(int)me rc:(BOOL)rc {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.rS(), rS);
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XCTAssertEqual(instruction.rB(), rB);
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XCTAssertEqual(instruction.mb<uint32_t>(), mb);
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XCTAssertEqual(instruction.me<uint32_t>(), me);
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XCTAssertEqual(!!instruction.rc(), rc);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation to:(int)to rA:(int)rA simm:(int)simm {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.to(), to);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.simm(), simm);
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}
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- (void)assert:(Instruction &)instruction operation:(Operation)operation crfD:(int)crfD l:(BOOL)l rA:(int)rA uimm:(int)uimm {
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XCTAssertEqual(instruction.operation, operation);
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XCTAssertEqual(instruction.crfD(), crfD);
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XCTAssertEqual(!!instruction.l(), l);
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XCTAssertEqual(instruction.rA(), rA);
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XCTAssertEqual(instruction.uimm(), uimm);
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}
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// MARK: - Decoder
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- (void)decode:(const uint32_t *)stream {
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InstructionSet::PowerPC::Decoder<InstructionSet::PowerPC::Model::MPC601> decoder;
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for(int c = 0; c < 32; c++) {
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instructions[c] = decoder.decode(stream[c]);
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}
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}
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// MARK: - Tests
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- (void)testSequence1 {
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const uint32_t sequence[] = {
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0x32eeefa5, 0xc2ee0786, 0x80ce552c, 0x88d5f02a,
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0xf8c2e801, 0xe83d5cdf, 0x7fa51fbb, 0xaacea8b0,
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0x7d4d4d21, 0x1314cf89, 0x47e0014b, 0xdf67566d,
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0xfb29a33e, 0x312cbf53, 0x706f1a15, 0xa87b7011,
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0x2107090c, 0xce04935e, 0x642e464a, 0x931e8eba,
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0xee396d5b, 0x4901183d, 0x31ccaa9a, 0x42b61a86,
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0x1ed4751d, 0x86af76e4, 0x151405a9, 0xca0ac015,
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0x60dd1f9d, 0xecff44f6, 0xf2c1110e, 0x9aa6653b,
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};
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[self decode:sequence];
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// addic r23,r14,-4187
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// lfs f23,1926(r14)
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// lwz r6,21804(r14)
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// lbz r6,-4054(r21)
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[self assert:instructions[0] operation:Operation::addic rD:23 rA:14 simm:-4187];
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[self assert:instructions[1] operation:Operation::lfs frD:23 rA:14 d:1926];
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[self assert:instructions[2] operation:Operation::lwz rD:6 rA:14 d:21804];
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[self assert:instructions[3] operation:Operation::lbz rD:6 rA:21 d:-4054];
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// .long 0xf8c2e801
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// .long 0xe83d5cdf
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// .long 0x7fa51fbb
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// lha r22,-22352(r14)
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[self assertUndefined:instructions[4]];
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[self assertUndefined:instructions[5]];
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[self assertUndefined:instructions[6]];
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[self assert:instructions[7] operation:Operation::lha rD:22 rA:14 d:-22352];
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// .long 0x7d4d4d21
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// .long 0x1314cf89
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// .long 0x47e0014b
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[self assertUndefined:instructions[8]];
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[self assertUndefined:instructions[9]];
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// CLK decodes this as sc because it ignores reserved bits; the disassembler
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// I used checks the reserved bits. For now: don't test.
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// XCTAssertEqual(instructions[10].operation, Operation::Undefined);
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// stfdu f27,22125(r7)
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// .long 0xfb29a33e
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// addic r9,r12,-16557
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// andi. r15,r3,6677
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[self assert:instructions[11] operation:Operation::stfdu frS:27 rA:7 d:22125];
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[self assertUndefined:instructions[12]];
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[self assert:instructions[13] operation:Operation::addic rD:9 rA:12 simm:-16557];
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[self assert:instructions[14] operation:Operation::andi_ rA:15 rS:3 uimm:6677];
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// lha r3,28689(r27)
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// subfic r8,r7,2316
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// lfdu f16,-27810(r4)
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// oris r14,r1,17994
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[self assert:instructions[15] operation:Operation::lha rD:3 rA:27 d:28689];
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[self assert:instructions[16] operation:Operation::subfic rD:8 rA:7 simm:2316];
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[self assert:instructions[17] operation:Operation::lfdu frD:16 rA:4 d:-27810];
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[self assert:instructions[18] operation:Operation::oris rA:14 rS:1 uimm:17994];
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// stw r24,-28998(r30)
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// .long 0xee396d5b
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// bl 0x01011890 [disassmebled at address 0x54]
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// addic r14,r12,-21862
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[self assert:instructions[19] operation:Operation::stw rS:24 rA:30 d:-28998];
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[self assertUndefined:instructions[20]];
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[self assert:instructions[21] operation:Operation::bx li:0x01011890 - 0x54 lk:TRUE aa:FALSE];
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[self assert:instructions[22] operation:Operation::addic rD:14 rA:12 simm:-21862];
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// .long 0x42b61a86 [10101]
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// mulli r22,r20,29981
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// lwzu r21,30436(r15)
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// .long 0x151405a9
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[self assertUndefined:instructions[23]];
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[self assert:instructions[24] operation:Operation::mulli rD:22 rA:20 simm:29981];
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[self assert:instructions[25] operation:Operation::lwzu rD:21 rA:15 d:30436];
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[self assertUndefined:instructions[26]];
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// lfd f16,-16363(r10)
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// ori r29,r6,8093
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// .long 0xecff44f6
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// .long 0xf2c1110e
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// stb r21,25915(r6)
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[self assert:instructions[27] operation:Operation::lfd frD:16 rA:10 d:-16363];
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[self assert:instructions[28] operation:Operation::ori rA:29 rS:6 uimm:8093];
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[self assertUndefined:instructions[29]];
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[self assertUndefined:instructions[30]];
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[self assert:instructions[31] operation:Operation::stb rS:21 rA:6 d:25915];
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}
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- (void)testSequence2 {
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const uint32_t sequence[] = {
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0x90252dae, 0x7429ee14, 0x618935bc, 0xd6c94af0,
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0xba1d295f, 0x649e3869, 0x6def742c, 0x5c64cdce,
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0x762d59ee, 0x565c8189, 0xc7c59f81, 0xce1157fd,
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0xc86aef59, 0x81325882, 0x1336fad6, 0xe1ddfa2b,
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0x18c60357, 0x4c122cb5, 0xccb1f749, 0xdbdcebc3,
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0x0fc60187, 0x117eb911, 0x80334c43, 0xe65371e8,
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0xa047c94d, 0xe671dd0b, 0xe07992bb, 0x6a332fe8,
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0xfc361c6b, 0x5e8b5a28, 0xb2b64a22, 0x045dd156,
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};
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[self decode:sequence];
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// stw r1,11694(r5)
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// andis. r9,r1,60948
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// ori r9,r12,13756
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// stfsu f22,19184(r9)
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[self assert:instructions[0] operation:Operation::stw rS:1 rA:5 d:11694];
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[self assert:instructions[1] operation:Operation::andis_ rA:9 rS:1 uimm:60948];
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[self assert:instructions[2] operation:Operation::ori rA:9 rS:12 uimm:13756];
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[self assert:instructions[3] operation:Operation::stfsu frS:22 rA:9 d:19184];
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// lmw r16,10591(r29)
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// oris r30,r4,14441
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// xoris r15,r15,29740
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// rlwnm r4,r3,r25,23,7
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[self assert:instructions[4] operation:Operation::lmw rD:16 rA:29 d:10591];
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[self assert:instructions[5] operation:Operation::oris rA:30 rS:4 uimm:14441];
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[self assert:instructions[6] operation:Operation::xoris rA:15 rS:15 uimm:29740];
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[self assert:instructions[7] operation:Operation::rlwnmx rA:4 rS:3 rB:25 mb:23 me:7 rc:FALSE];
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// andis. r13,r17,23022
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// rlwinm. r28,r18,16,6,4
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// lfsu f30,-24703(r5)
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// lfdu f16,22525(r17)
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[self assert:instructions[8] operation:Operation::andis_ rA:13 rS:17 uimm:23022];
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[self assert:instructions[9] operation:Operation::rlwinmx rA:28 rS:18 rB:16 mb:6 me:4 rc:TRUE];
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[self assert:instructions[10] operation:Operation::lfsu frD:30 rA:5 d:-24703];
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[self assert:instructions[11] operation:Operation::lfdu frD:16 rA:17 d:22525];
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// lfd f3,-4263(r10)
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// lwz r9,22658(r18)
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// .long 0x1336fad6
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// .long 0xe1ddfa2b
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[self assert:instructions[12] operation:Operation::lfd frD:3 rA:10 d:-4263];
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[self assert:instructions[13] operation:Operation::lwz rD:9 rA:18 d:22658];
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[self assertUndefined:instructions[14]];
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[self assertUndefined:instructions[15]];
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// .long 0x18c60357
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// .long 0x4c122cb5
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// lfdu f5,-2231(r17)
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// stfd f30,-5181(r28)
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[self assertUndefined:instructions[16]];
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[self assertUndefined:instructions[17]];
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[self assert:instructions[18] operation:Operation::lfdu frD:5 rA:17 d:-2231];
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[self assert:instructions[19] operation:Operation::stfd frD:30 rA:28 d:-5181];
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// twi 30,r6,391
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// .long 0x117eb911
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// lwz r1,19523(r19)
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// .long 0xe65371e8
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[self assert:instructions[20] operation:Operation::twi to:30 rA:6 simm:391];
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[self assertUndefined:instructions[21]];
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[self assert:instructions[22] operation:Operation::lwz rD:1 rA:19 d:19523];
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[self assertUndefined:instructions[23]];
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// lhz r2,-14003(r7)
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// .long 0xe671dd0b
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// .long 0xe07992bb
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// xori r19,r17,12264
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[self assert:instructions[24] operation:Operation::lhz rD:2 rA:7 d:-14003];
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[self assertUndefined:instructions[25]];
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[self assertUndefined:instructions[26]];
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[self assert:instructions[27] operation:Operation::xori rA:19 rS:17 uimm:12264];
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// .long 0xfc361c6b
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// rlwnm r11,r20,r11,8,20
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// sth r21,18978(r22)
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// .long 0x45dd156
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// [self assertUndefined:instructions[28]]; // Disabled due to reserved field; I'm decoding this as faddx.
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[self assert:instructions[29] operation:Operation::rlwnmx rA:11 rS:20 rB:11 mb:8 me:20 rc:FALSE];
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[self assert:instructions[30] operation:Operation::sth rS:21 rA:22 d:18978];
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[self assertUndefined:instructions[31]];
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}
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- (void)testSequence3 {
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const uint32_t sequence[] = {
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0xbcaf3520, 0xfa9df12d, 0xc631efca, 0xa3e7f409,
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0x3ddca273, 0x3cfb234d, 0x551dc325, 0x8c1a0f37,
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0x5b3ca99b, 0xce08cc1e, 0x7b1dfd3a, 0xf19aee7c,
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0x52c852e9, 0xc681c0c1, 0xd3b1fda5, 0xe2b401cb,
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0x433cb83d, 0x54412f41, 0x532d624a, 0x0b3117c5,
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0x988144ba, 0xc7a96ad0, 0x28331474, 0x5620c367,
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0xab0a2607, 0xe826acf4, 0x41969154, 0x6471d09f,
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0x6a25f04f, 0x4a15996d, 0x272c96ef, 0xab3171a9,
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};
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[self decode:sequence];
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// stmw r5,13600(r15)
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// .long 0xfa9df12d
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// lfsu f17,-4150(r17)
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// lhz r31,-3063(r7)
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[self assert:instructions[0] operation:Operation::stmw rS:5 rA:15 d:13600];
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[self assertUndefined:instructions[1]];
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[self assert:instructions[2] operation:Operation::lfsu frD:17 rA:17 d:-4150];
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[self assert:instructions[3] operation:Operation::lhz rD:31 rA:7 d:-3063];
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// addis r14,r28,-23949
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// addis r7,r27,9037
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// rlwinm. r29,r8,24,12,18
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// lbzu r0,3895(r26)
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[self assert:instructions[4] operation:Operation::addis rD:14 rA:28 simm:-23949];
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[self assert:instructions[5] operation:Operation::addis rD:7 rA:27 simm:9037];
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[self assert:instructions[6] operation:Operation::rlwinmx rA:29 rS:8 rB:24 mb:12 me:18 rc:TRUE];
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[self assert:instructions[7] operation:Operation::lbzu rD:0 rA:26 d:3895];
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// rlmi. r28,r25,r21,6,13
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// lfdu f16,-13282(r8)
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// .long 0x7b1dfd3a
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// .long 0xf19aee7c
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[self assert:instructions[8] operation:Operation::rlmix rA:28 rS:25 rB:21 mb:6 me:13 rc:TRUE];
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[self assert:instructions[9] operation:Operation::lfdu frD:16 rA:8 d:-13282];
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[self assertUndefined:instructions[10]];
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[self assertUndefined:instructions[11]];
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// rlwimi. r8,r22,10,11,20
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// lfsu f20,-16191(r1)
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// stfs f29,-603(r17)
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// .long 0xe2b401cb
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[self assert:instructions[12] operation:Operation::rlwimix rA:8 rS:22 rB:10 mb:11 me:20 rc:TRUE];
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[self assert:instructions[13] operation:Operation::lfsu frD:20 rA:1 d:-16191];
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[self assert:instructions[14] operation:Operation::stfs frS:29 rA:17 d:-603];
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[self assertUndefined:instructions[15]];
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// .long 0x433cb83d
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// rlwinm. r1,r2,5,29,0
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// rlwimi r13,r25,12,9,5
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// .long 0xb3117c5
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[self assertUndefined:instructions[16]];
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[self assert:instructions[17] operation:Operation::rlwinmx rA:1 rS:2 rB:5 mb:29 me:0 rc:TRUE];
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[self assert:instructions[18] operation:Operation::rlwimix rA:13 rS:25 rB:12 mb:9 me:5 rc:FALSE];
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[self assertUndefined:instructions[19]];
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// stb r4,17594(r1)
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// lfsu f29,27344(r9)
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// cmpli cr0,1,r19,5236
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// rlwinm. r0,r17,24,13,19
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[self assert:instructions[20] operation:Operation::stb rS:4 rA:1 d:17594];
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[self assert:instructions[21] operation:Operation::lfsu frD:29 rA:9 d:27344];
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[self assert:instructions[22] operation:Operation::cmpli crfD:0 l:TRUE rA:19 uimm:5236];
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[self assert:instructions[23] operation:Operation::rlwinmx rA:0 rS:17 rB:24 mb:13 me:19 rc:TRUE];
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// lha r24,9735(r10)
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// .long 0xe826acf4
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// beq+ cr5,0xffffffffffff91bc [at address 0x68]
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// oris r17,r3,53407
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[self assert:instructions[24] operation:Operation::lha rD:24 rA:10 d:9735];
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[self assertUndefined:instructions[25]];
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[self assert:instructions[26] operation:Operation::bcx bo:12 bi:22 bd:0xffff91bc - 0x68 lk:FALSE aa:FALSE];
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[self assert:instructions[27] operation:Operation::oris rA:17 rS:3 uimm:53407];
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// xori r5,r17,61519
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// bl 0xfffffffffe1599e0 [at address 0x74]
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// dozi r25,r12,-26897
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// lha r25,29097(r17)
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[self assert:instructions[28] operation:Operation::xori rA:5 rS:17 uimm:61519];
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[self assert:instructions[29] operation:Operation::bx li:0xfe1599e0 - 0x74 lk:TRUE aa:FALSE];
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[self assert:instructions[30] operation:Operation::dozi rD:25 rA:12 simm:-26897];
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[self assert:instructions[31] operation:Operation::lha rD:25 rA:17 d:29097];
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}
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@end
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