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393 lines
10 KiB
C++
393 lines
10 KiB
C++
//
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// Instruction.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/04/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_68k_Instruction_hpp
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#define InstructionSets_68k_Instruction_hpp
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#include <cstdint>
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#include "Model.hpp"
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namespace InstructionSet {
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namespace M68k {
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enum class Operation: uint8_t {
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Undefined,
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NOP,
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ABCD, SBCD, NBCD,
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ADDb, ADDw, ADDl,
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ADDAw, ADDAl,
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ADDXb, ADDXw, ADDXl,
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SUBb, SUBw, SUBl,
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SUBAw, SUBAl,
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SUBXb, SUBXw, SUBXl,
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MOVEb, MOVEw, MOVEl,
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MOVEAw, MOVEAl,
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LEA, PEA,
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MOVEtoSR, MOVEfromSR,
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MOVEtoCCR,
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MOVEtoUSP, MOVEfromUSP,
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ORItoSR, ORItoCCR,
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ANDItoSR, ANDItoCCR,
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EORItoSR, EORItoCCR,
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BTST, BCLR,
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BCHG, BSET,
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CMPb, CMPw, CMPl,
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CMPAw, CMPAl,
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TSTb, TSTw, TSTl,
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JMP,
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JSR, RTS,
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DBcc,
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Scc,
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Bccb, Bccw, Bccl,
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BSRb, BSRw, BSRl,
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CLRb, CLRw, CLRl,
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NEGXb, NEGXw, NEGXl,
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NEGb, NEGw, NEGl,
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ASLb, ASLw, ASLl, ASLm,
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ASRb, ASRw, ASRl, ASRm,
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LSLb, LSLw, LSLl, LSLm,
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LSRb, LSRw, LSRl, LSRm,
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ROLb, ROLw, ROLl, ROLm,
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RORb, RORw, RORl, RORm,
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ROXLb, ROXLw, ROXLl, ROXLm,
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ROXRb, ROXRw, ROXRl, ROXRm,
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MOVEMl, MOVEMw,
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MOVEPl, MOVEPw,
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ANDb, ANDw, ANDl,
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EORb, EORw, EORl,
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NOTb, NOTw, NOTl,
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ORb, ORw, ORl,
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MULU, MULS,
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DIVU, DIVS,
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RTE, RTR,
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TRAP, TRAPV,
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CHK,
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EXG, SWAP,
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TAS,
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EXTbtow, EXTwtol,
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LINKw, UNLINK,
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STOP, RESET,
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Max = RESET
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};
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template <Model model>
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constexpr bool requires_supervisor(Operation op) {
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switch(op) {
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case Operation::MOVEfromSR:
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if constexpr (model == Model::M68000) {
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return false;
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}
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[[fallthrough]];
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case Operation::ORItoSR: case Operation::ANDItoSR:
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case Operation::EORItoSR: case Operation::RTE:
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case Operation::RESET: case Operation::STOP:
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case Operation::MOVEtoUSP: case Operation::MOVEfromUSP:
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return true;
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default:
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return false;
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}
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}
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enum class DataSize {
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Byte = 0,
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Word = 1,
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LongWord = 2,
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};
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/// Classifies operations by the size of their memory accesses, if any.
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constexpr DataSize size(Operation operation) {
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switch(operation) {
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// These are given a value arbitrarily, to
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// complete the switch statement.
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case Operation::Undefined:
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case Operation::NOP:
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case Operation::STOP:
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case Operation::RESET:
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case Operation::RTE: case Operation::RTR:
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case Operation::TRAP:
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case Operation::TRAPV:
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case Operation::ABCD: case Operation::SBCD:
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case Operation::NBCD:
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case Operation::ADDb: case Operation::ADDXb:
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case Operation::SUBb: case Operation::SUBXb:
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case Operation::MOVEb:
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case Operation::ORItoCCR:
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case Operation::ANDItoCCR:
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case Operation::EORItoCCR:
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case Operation::BTST: case Operation::BCLR:
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case Operation::BCHG: case Operation::BSET:
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case Operation::CMPb: case Operation::TSTb:
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case Operation::Bccb: case Operation::BSRb:
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case Operation::CLRb:
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case Operation::NEGXb: case Operation::NEGb:
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case Operation::ASLb: case Operation::ASRb:
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case Operation::LSLb: case Operation::LSRb:
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case Operation::ROLb: case Operation::RORb:
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case Operation::ROXLb: case Operation::ROXRb:
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case Operation::ANDb: case Operation::EORb:
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case Operation::NOTb: case Operation::ORb:
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case Operation::CHK:
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case Operation::TAS:
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return DataSize::Byte;
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case Operation::ADDw: case Operation::ADDAw:
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case Operation::ADDXw: case Operation::SUBw:
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case Operation::SUBAw: case Operation::SUBXw:
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case Operation::MOVEw: case Operation::MOVEAw:
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case Operation::ORItoSR:
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case Operation::ANDItoSR:
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case Operation::EORItoSR:
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case Operation::MOVEtoSR:
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case Operation::MOVEfromSR:
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case Operation::MOVEtoCCR:
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case Operation::CMPw: case Operation::CMPAw:
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case Operation::TSTw:
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case Operation::DBcc: case Operation::Scc:
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case Operation::Bccw: case Operation::BSRw:
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case Operation::CLRw:
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case Operation::NEGXw: case Operation::NEGw:
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case Operation::ASLw: case Operation::ASLm:
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case Operation::ASRw: case Operation::ASRm:
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case Operation::LSLw: case Operation::LSLm:
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case Operation::LSRw: case Operation::LSRm:
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case Operation::ROLw: case Operation::ROLm:
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case Operation::RORw: case Operation::RORm:
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case Operation::ROXLw: case Operation::ROXLm:
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case Operation::ROXRw: case Operation::ROXRm:
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case Operation::MOVEMw:
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case Operation::MOVEPw:
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case Operation::ANDw: case Operation::EORw:
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case Operation::NOTw: case Operation::ORw:
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case Operation::DIVU: case Operation::DIVS:
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case Operation::MULU: case Operation::MULS:
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case Operation::EXTbtow:
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case Operation::LINKw:
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return DataSize::Word;
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case Operation::ADDl: case Operation::ADDAl:
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case Operation::ADDXl: case Operation::SUBl:
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case Operation::SUBAl: case Operation::SUBXl:
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case Operation::MOVEl: case Operation::MOVEAl:
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case Operation::LEA: case Operation::PEA:
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case Operation::EXG: case Operation::SWAP:
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case Operation::MOVEtoUSP:
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case Operation::MOVEfromUSP:
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case Operation::CMPl: case Operation::CMPAl:
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case Operation::TSTl:
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case Operation::JMP: case Operation::JSR:
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case Operation::RTS:
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case Operation::Bccl: case Operation::BSRl:
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case Operation::CLRl:
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case Operation::NEGXl: case Operation::NEGl:
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case Operation::ASLl: case Operation::ASRl:
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case Operation::LSLl: case Operation::LSRl:
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case Operation::ROLl: case Operation::RORl:
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case Operation::ROXLl: case Operation::ROXRl:
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case Operation::MOVEMl:
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case Operation::MOVEPl:
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case Operation::ANDl: case Operation::EORl:
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case Operation::NOTl: case Operation::ORl:
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case Operation::EXTwtol:
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case Operation::UNLINK:
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return DataSize::LongWord;
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}
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}
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template <Operation op>
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constexpr uint32_t quick(uint16_t instruction) {
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switch(op) {
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case Operation::Bccb:
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case Operation::BSRb:
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case Operation::MOVEl: return uint32_t(int8_t(instruction));
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case Operation::TRAP: return uint32_t(instruction & 15);
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default: {
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uint32_t value = (instruction >> 9) & 7;
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value |= (value - 1)&8;
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return value;
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}
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}
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}
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constexpr uint32_t quick(Operation op, uint16_t instruction) {
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switch(op) {
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case Operation::MOVEl: return quick<Operation::MOVEl>(instruction);
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case Operation::Bccb: return quick<Operation::Bccb>(instruction);
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case Operation::BSRb: return quick<Operation::BSRb>(instruction);
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case Operation::TRAP: return quick<Operation::TRAP>(instruction);
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default:
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// ADDw is arbitrary; anything other than those listed above will do.
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return quick<Operation::ADDw>(instruction);
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}
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}
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/// Indicates the addressing mode applicable to an operand.
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///
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/// Implementation notes:
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///
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/// Those entries starting 0b00 or 0b01 are mapped as per the 68000's native encoding;
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/// those starting 0b00 are those which are indicated directly by a mode field and those starting
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/// 0b01 are those which are indicated by a register field given a mode of 0b111. The only minor
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/// exception is AddressRegisterDirect, which exists on a 68000 but isn't specifiable by a
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/// mode and register, it's contextual based on the instruction.
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///
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/// Those modes starting in 0b10 are the various extended addressing modes introduced as
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/// of the 68020, which can be detected only after interpreting an extension word. At the
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/// Preinstruction stage:
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///
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/// * AddressRegisterIndirectWithIndexBaseDisplacement, MemoryIndirectPostindexed
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/// and MemoryIndirectPreindexed will have been partially decoded as
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/// AddressRegisterIndirectWithIndex8bitDisplacement; and
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/// * ProgramCounterIndirectWithIndexBaseDisplacement,
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/// ProgramCounterMemoryIndirectPostindexed and
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/// ProgramCounterMemoryIndirectPreindexed will have been partially decoded
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/// as ProgramCounterIndirectWithIndex8bitDisplacement.
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enum class AddressingMode: uint8_t {
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/// No adddressing mode; this operand doesn't exist.
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None = 0b01'101,
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/// Dn
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DataRegisterDirect = 0b00'000,
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/// An
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AddressRegisterDirect = 0b00'001,
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/// (An)
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AddressRegisterIndirect = 0b00'010,
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/// (An)+
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AddressRegisterIndirectWithPostincrement = 0b00'011,
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/// -(An)
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AddressRegisterIndirectWithPredecrement = 0b00'100,
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/// (d16, An)
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AddressRegisterIndirectWithDisplacement = 0b00'101,
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/// (d8, An, Xn)
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AddressRegisterIndirectWithIndex8bitDisplacement = 0b00'110,
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/// (bd, An, Xn)
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AddressRegisterIndirectWithIndexBaseDisplacement = 0b10'000,
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/// ([bd, An, Xn], od)
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MemoryIndirectPostindexed = 0b10'001,
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/// ([bd, An], Xn, od)
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MemoryIndirectPreindexed = 0b10'010,
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/// (d16, PC)
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ProgramCounterIndirectWithDisplacement = 0b01'010,
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/// (d8, PC, Xn)
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ProgramCounterIndirectWithIndex8bitDisplacement = 0b01'011,
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/// (bd, PC, Xn)
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ProgramCounterIndirectWithIndexBaseDisplacement = 0b10'011,
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/// ([bd, PC, Xn], od)
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ProgramCounterMemoryIndirectPostindexed = 0b10'100,
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/// ([bc, PC], Xn, od)
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ProgramCounterMemoryIndirectPreindexed = 0b10'101,
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/// (xxx).W
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AbsoluteShort = 0b01'000,
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/// (xxx).L
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AbsoluteLong = 0b01'001,
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/// #
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ImmediateData = 0b01'100,
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/// .q; value is embedded in the opcode.
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Quick = 0b01'110,
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};
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/*!
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A preinstruction is as much of an instruction as can be decoded with
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only the first instruction word — i.e. an operation, and:
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* on the 68000 and 68010, the complete addressing modes;
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* on subsequent, a decent proportion of the addressing mode. See
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the notes on @c AddressingMode for potential aliasing.
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*/
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class Preinstruction {
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public:
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Operation operation = Operation::Undefined;
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// Instructions come with 0, 1 or 2 operands;
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// the getters below act to provide a list of operands
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// that is terminated by an AddressingMode::None.
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//
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// For two-operand instructions, argument 0 is a source
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// and argument 1 is a destination.
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//
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// For one-operand instructions, only argument 0 will
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// be provided, and will be a source and/or destination as
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// per the semantics of the operation.
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template <int index> AddressingMode mode() const {
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if constexpr (index > 1) {
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return AddressingMode::None;
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}
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return AddressingMode(operands_[index] & 0x1f);
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}
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template <int index> int reg() const {
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if constexpr (index > 1) {
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return 0;
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}
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return operands_[index] >> 5;
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}
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bool requires_supervisor() {
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return flags_ & 0x80;
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}
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DataSize size() {
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return DataSize(flags_ & 0x7f);
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}
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private:
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uint8_t operands_[2] = { uint8_t(AddressingMode::None), uint8_t(AddressingMode::None)};
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uint8_t flags_ = 0;
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public:
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Preinstruction(
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Operation operation,
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AddressingMode op1_mode, int op1_reg,
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AddressingMode op2_mode, int op2_reg,
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bool is_supervisor,
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DataSize size) : operation(operation)
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{
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operands_[0] = uint8_t(op1_mode) | uint8_t(op1_reg << 5);
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operands_[1] = uint8_t(op2_mode) | uint8_t(op2_reg << 5);
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flags_ = (is_supervisor ? 0x80 : 0x00) | uint8_t(size);
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}
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Preinstruction() {}
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};
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}
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}
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#endif /* InstructionSets_68k_Instruction_hpp */
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