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432 lines
12 KiB
C++
432 lines
12 KiB
C++
//
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// 8530.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 07/06/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#include "z8530.hpp"
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#ifndef NDEBUG
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#define NDEBUG
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#endif
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#define LOG_PREFIX "[SCC] "
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#include "../../Outputs/Log.hpp"
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using namespace Zilog::SCC;
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void z8530::reset() {
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// TODO.
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}
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bool z8530::get_interrupt_line() const {
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return
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(master_interrupt_control_ & 0x8) &&
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(
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channels_[0].get_interrupt_line() ||
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channels_[1].get_interrupt_line()
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);
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}
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/*
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Per the standard defined in the header file, this implementation follows
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an addressing convention of:
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A0 = A/B (i.e. channel select)
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A1 = C/D (i.e. control or data)
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*/
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std::uint8_t z8530::read(int address) {
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if(address & 2) {
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// Read data register for channel.
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return channels_[address & 1].read(true, pointer_);
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} else {
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// Read control register for channel.
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uint8_t result = 0;
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switch(pointer_) {
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default:
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result = channels_[address & 1].read(false, pointer_);
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break;
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case 2: // Handled non-symmetrically between channels.
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if(address & 1) {
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LOG("Unimplemented: register 2 status bits");
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} else {
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result = interrupt_vector_;
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// Modify the vector if permitted.
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// if(master_interrupt_control_ & 1) {
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for(int port = 0; port < 2; ++port) {
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// TODO: the logic below assumes that DCD is the only implemented interrupt. Fix.
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if(channels_[port].get_interrupt_line()) {
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const uint8_t shift = 1 + 3*((master_interrupt_control_ & 0x10) >> 4);
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const uint8_t mask = uint8_t(~(7 << shift));
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result = uint8_t(
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(result & mask) |
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((1 | ((port == 1) ? 4 : 0)) << shift)
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);
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break;
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}
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}
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// }
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}
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break;
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}
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// Cf. the two-step control register selection process in ::write. Since this
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// definitely wasn't a *write* to register 0, it follows that the next selected
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// control register will be 0.
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pointer_ = 0;
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update_delegate();
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return result;
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}
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return 0x00;
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}
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void z8530::write(int address, std::uint8_t value) {
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if(address & 2) {
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// Write data register for channel. This is completely independent
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// of whatever is going on over in the control realm.
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channels_[address & 1].write(true, pointer_, value);
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} else {
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// Write control register for channel; there's a two-step sequence
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// here for the programmer. Initially the selected register
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// (i.e. `pointer_`) is zero. That register includes a field to
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// set the next selected register. After any other register has
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// been written to, register 0 is selected again.
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// Most registers are per channel, but a couple are shared;
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// sever them here, send the rest to the appropriate chnanel.
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switch(pointer_) {
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default:
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channels_[address & 1].write(false, pointer_, value);
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break;
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case 2: // Interrupt vector register; used only by Channel B.
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// So there's only one of these.
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interrupt_vector_ = value;
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LOG("Interrupt vector set to " << PADHEX(2) << int(value));
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break;
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case 9: // Master interrupt and reset register; there is also only one of these.
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LOG("Master interrupt and reset register: " << PADHEX(2) << int(value));
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master_interrupt_control_ = value;
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break;
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}
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// The pointer number resets to 0 after every access, but if it is zero
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// then crib at least the next set of pointer bits (which, similarly, are shared
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// between the two channels).
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if(pointer_) {
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pointer_ = 0;
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} else {
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// The lowest three bits are the lowest three bits of the pointer.
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pointer_ = value & 7;
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// If the command part of the byte is a 'point high', also set the
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// top bit of the pointer. Channels themselves therefore need not
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// (/should not) respond to the point high command.
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if(((value >> 3)&7) == 1) {
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pointer_ |= 8;
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}
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}
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}
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update_delegate();
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}
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void z8530::set_dcd(int port, bool level) {
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channels_[port].set_dcd(level);
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update_delegate();
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}
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// MARK: - Channel implementations
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uint8_t z8530::Channel::read(bool data, uint8_t pointer) {
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// If this is a data read, just return it.
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if(data) {
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return data_;
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} else {
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LOG("Control read from register " << int(pointer));
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// Otherwise, this is a control read...
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switch(pointer) {
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default:
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return 0x00;
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case 0x0: // Read Register 0; see p.37 (PDF p.45).
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// b0: Rx character available.
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// b1: zero count.
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// b2: Tx buffer empty.
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// b3: DCD.
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// b4: sync/hunt.
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// b5: CTS.
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// b6: Tx underrun/EOM.
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// b7: break/abort.
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return dcd_ ? 0x8 : 0x0;
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case 0x1: // Read Register 1; see p.37 (PDF p.45).
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// b0: all sent.
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// b1: residue code 0.
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// b2: residue code 1.
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// b3: residue code 2.
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// b4: parity error.
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// b5: Rx overrun error.
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// b6: CRC/framing error.
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// b7: end of frame (SDLC).
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return 0x01;
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case 0x2: // Read Register 2; see p.37 (PDF p.45).
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// Interrupt vector — modified by status information in B channel.
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return 0x00;
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case 0x3: // Read Register 3; see p.37 (PDF p.45).
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// B channel: all bits are 0.
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// A channel:
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// b0: Channel B ext/status IP.
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// b1: Channel B Tx IP.
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// b2: Channel B Rx IP.
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// b3: Channel A ext/status IP.
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// b4: Channel A Tx IP.
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// b5: Channel A Rx IP.
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// b6, b7: 0.
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return 0x00;
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case 0xa: // Read Register 10; see p.37 (PDF p.45).
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// b0: 0
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// b1: On loop.
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// b2: 0
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// b3: 0
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// b4: Loop sending.
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// b5: 0
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// b6: Two clocks missing.
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// b7: One clock missing.
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return 0x00;
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case 0xc: // Read Register 12; see p.37 (PDF p.45).
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// Lower byte of time constant.
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return 0x00;
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case 0xd: // Read Register 13; see p.38 (PDF p.46).
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// Upper byte of time constant.
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return 0x00;
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case 0xf: // Read Register 15; see p.38 (PDF p.46).
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// External interrupt status:
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// b0: 0
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// b1: Zero count.
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// b2: 0
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// b3: DCD.
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// b4: Sync/hunt.
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// b5: CTS.
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// b6: Tx underrun/EOM.
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// b7: Break/abort.
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return external_interrupt_status_;
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}
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}
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return 0x00;
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}
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void z8530::Channel::write(bool data, uint8_t pointer, uint8_t value) {
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if(data) {
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data_ = value;
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return;
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} else {
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LOG("Control write: " << PADHEX(2) << int(value) << " to register " << int(pointer));
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switch(pointer) {
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default:
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LOG("Unrecognised control write: " << PADHEX(2) << int(value) << " to register " << int(pointer));
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break;
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case 0x0: // Write register 0 — CRC reset and other functions.
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// Decode CRC reset instructions.
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switch(value >> 6) {
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default: /* Do nothing. */ break;
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case 1:
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LOG("TODO: reset Rx CRC checker.");
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break;
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case 2:
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LOG("TODO: reset Tx CRC checker.");
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break;
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case 3:
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LOG("TODO: reset Tx underrun/EOM latch.");
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break;
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}
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// Decode command code.
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switch((value >> 3)&7) {
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default: /* Do nothing. */ break;
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case 2:
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// LOG("reset ext/status interrupts.");
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external_status_interrupt_ = false;
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external_interrupt_status_ = 0;
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break;
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case 3:
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LOG("TODO: send abort (SDLC).");
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break;
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case 4:
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LOG("TODO: enable interrupt on next Rx character.");
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break;
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case 5:
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LOG("TODO: reset Tx interrupt pending.");
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break;
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case 6:
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LOG("TODO: reset error.");
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break;
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case 7:
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LOG("TODO: reset highest IUS.");
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break;
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}
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break;
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case 0x1: // Write register 1 — Transmit/Receive Interrupt and Data Transfer Mode Definition.
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interrupt_mask_ = value;
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/*
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b7 = 0 => Wait/Request output is inactive; 1 => output is informative.
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b6 = Wait/request output is for...
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0 => wait: floating when inactive, low if CPU is attempting to transfer data the SCC isn't yet ready for.
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1 => request: high if inactive, low if SCC is ready to transfer data.
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b5 = 1 => wait/request is relative to read buffer; 0 => relative to write buffer.
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b4/b3:
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00 = disable receive interrupt
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01 = interrupt on first character or special condition
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10 = interrupt on all characters and special conditions
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11 = interrupt only upon special conditions.
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b2 = 1 => parity error is a special condition; 0 => it isn't.
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b1 = 1 => transmit buffer empty interrupt is enabled; 0 => it isn't.
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b0 = 1 => external interrupt is enabled; 0 => it isn't.
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*/
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LOG("Interrupt mask: " << PADHEX(2) << int(value));
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break;
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case 0x2: // Write register 2 - interrupt vector.
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break;
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case 0x3: { // Write register 3 — Receive Parameters and Control.
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// Get bit count.
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int receive_bit_count = 8;
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switch(value >> 6) {
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default: receive_bit_count = 5; break;
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case 1: receive_bit_count = 7; break;
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case 2: receive_bit_count = 6; break;
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case 3: receive_bit_count = 8; break;
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}
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LOG("Receive bit count: " << receive_bit_count);
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(void)receive_bit_count;
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/*
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b7,b6:
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00 = 5 receive bits per character
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01 = 7 bits
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10 = 6 bits
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11 = 8 bits
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b5 = 1 => DCD and CTS outputs are set automatically; 0 => they're inputs to read register 0.
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(DCD is ignored in local loopback; CTS is ignored in both auto echo and local loopback).
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b4: enter hunt mode (if set to 1, presumably?)
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b3 = 1 => enable receiver CRC generation; 0 => don't.
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b2: address search mode (SDLC)
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b1: sync character load inhibit.
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b0: Rx enable.
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*/
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} break;
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case 0x4: // Write register 4 — Transmit/Receive Miscellaneous Parameters and Modes.
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// Bits 0 and 1 select parity mode.
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if(!(value&1)) {
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parity_ = Parity::Off;
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} else {
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parity_ = (value&2) ? Parity::Even : Parity::Odd;
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}
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// Bits 2 and 3 select stop bits.
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switch((value >> 2)&3) {
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default: stop_bits_ = StopBits::Synchronous; break;
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case 1: stop_bits_ = StopBits::OneBit; break;
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case 2: stop_bits_ = StopBits::OneAndAHalfBits; break;
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case 3: stop_bits_ = StopBits::TwoBits; break;
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}
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// Bits 4 and 5 pick a sync mode.
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switch((value >> 4)&3) {
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default: sync_mode_ = Sync::Monosync; break;
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case 1: sync_mode_ = Sync::Bisync; break;
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case 2: sync_mode_ = Sync::SDLC; break;
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case 3: sync_mode_ = Sync::External; break;
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}
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// Bits 6 and 7 select a clock rate multiplier, unless synchronous
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// mode is enabled (and this is ignored if sync mode is external).
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if(stop_bits_ == StopBits::Synchronous) {
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clock_rate_multiplier_ = 1;
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} else {
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switch((value >> 6)&3) {
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default: clock_rate_multiplier_ = 1; break;
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case 1: clock_rate_multiplier_ = 16; break;
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case 2: clock_rate_multiplier_ = 32; break;
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case 3: clock_rate_multiplier_ = 64; break;
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}
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}
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break;
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case 0x5:
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// b7: DTR
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// b6/b5:
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// 00 = Tx 5 bits (or less) per character
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// 01 = Tx 7 bits per character
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// 10 = Tx 6 bits per character
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// 11 = Tx 8 bits per character
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// b4: send break.
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// b3: Tx enable.
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// b2: SDLC (if 0) / CRC-16 (if 1)
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// b1: RTS
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// b0: Tx CRC enable.
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break;
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case 0x6:
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break;
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case 0xf: // Write register 15 — External/Status Interrupt Control.
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external_interrupt_mask_ = value;
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break;
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}
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}
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}
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void z8530::Channel::set_dcd(bool level) {
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if(dcd_ == level) return;
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dcd_ = level;
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if(external_interrupt_mask_ & 0x8) {
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external_status_interrupt_ = true;
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external_interrupt_status_ |= 0x8;
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}
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}
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bool z8530::Channel::get_interrupt_line() const {
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return
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(interrupt_mask_ & 1) && external_status_interrupt_;
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// TODO: other potential causes of an interrupt.
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}
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/*!
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Evaluates the new level of the interrupt line and notifies the delegate if
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both: (i) there is one; and (ii) the interrupt line has changed since last
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the delegate was notified.
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*/
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void z8530::update_delegate() {
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const bool interrupt_line = get_interrupt_line();
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if(interrupt_line != previous_interrupt_line_) {
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previous_interrupt_line_ = interrupt_line;
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if(delegate_) delegate_->did_change_interrupt_status(this, interrupt_line);
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}
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}
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