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363 lines
11 KiB
C++
363 lines
11 KiB
C++
//
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// 68000Storage.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 08/03/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#ifndef MC68000Storage_h
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#define MC68000Storage_h
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class ProcessorStorage {
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public:
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ProcessorStorage();
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protected:
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RegisterPair32 data_[8];
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RegisterPair32 address_[8];
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RegisterPair32 program_counter_;
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RegisterPair32 stack_pointers_[2]; // [0] = user stack pointer; [1] = supervisor; the values from here
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// are copied into/out of address_[7] upon mode switches.
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RegisterPair32 prefetch_queue_; // Each word will go into the low part of the word, then proceed upward.
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bool dtack_ = true;
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// Various status bits.
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int is_supervisor_;
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int interrupt_level_;
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uint_fast32_t zero_result_; // The zero flag is set if this value is zero.
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uint_fast32_t carry_flag_; // The carry flag is set if this value is non-zero.
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uint_fast32_t extend_flag_; // The extend flag is set if this value is non-zero.
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uint_fast32_t overflow_flag_; // The overflow flag is set if this value is non-zero.
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uint_fast32_t negative_flag_; // The negative flag is set if this value is non-zero.
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uint_fast32_t trace_flag_; // The trace flag is set if this value is non-zero.
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// Generic sources and targets for memory operations;
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// by convention: [0] = source, [1] = destination.
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RegisterPair32 effective_address_[2];
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RegisterPair32 source_bus_data_[1];
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RegisterPair32 destination_bus_data_[1];
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HalfCycles half_cycles_left_to_run_;
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enum class Operation {
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None,
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ABCD, SBCD,
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ADDb, ADDw, ADDl,
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SUBb, SUBw, SUBl,
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ADDAw, ADDAl,
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SUBAw, SUBAl,
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MOVEb, MOVEw, MOVEl, MOVEq,
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MOVEAw, MOVEAl,
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MOVEtoSR, MOVEfromSR,
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MOVEtoCCR,
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CMPb, CMPw, CMPl,
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BTSTb, BTSTl,
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JMP,
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BRA, Bcc,
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DBcc,
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CLRb, CLRw, CLRl,
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NEGXb, NEGXw, NEGXl,
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NEGb, NEGw, NEGl,
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NOTb, NOTw, NOTl,
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ASLb, ASLw, ASLl, ASLm,
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ASRb, ASRw, ASRl, ASRm,
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LSLb, LSLw, LSLl, LSLm,
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LSRb, LSRw, LSRl, LSRm,
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ROLb, ROLw, ROLl, ROLm,
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RORb, RORw, RORl, RORm,
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ROXLb, ROXLw, ROXLl, ROXLm,
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ROXRb, ROXRw, ROXRl, ROXRm,
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MOVEMtoRl, MOVEMtoRw,
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MOVEMtoMl, MOVEMtoMw,
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Scc,
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TSTb, TSTw, TSTl,
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};
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/*!
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Bus steps are sequences of things to communicate to the bus.
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Standard behaviour is: (i) perform microcycle; (ii) perform action.
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*/
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struct BusStep {
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Microcycle microcycle;
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enum class Action {
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None,
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/// Performs effective_address_[0] += 2.
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IncrementEffectiveAddress0,
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/// Performs effective_address_[1] += 2.
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IncrementEffectiveAddress1,
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/// Performs effective_address_[0] -= 2.
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DecrementEffectiveAddress0,
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/// Performs effective_address_[1] -= 2.
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DecrementEffectiveAddress1,
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/// Performs program_counter_ += 2.
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IncrementProgramCounter,
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/// Copies prefetch_queue_[1] to prefetch_queue_[0].
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AdvancePrefetch,
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/*!
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Terminates an atomic program; if nothing else is pending, schedules the next instruction.
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This action is special in that it usurps any included microcycle. So any Step with this
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as its action acts as an end-of-list sentinel.
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*/
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ScheduleNextProgram
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} action = Action::None;
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inline bool operator ==(const BusStep &rhs) const {
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if(action != rhs.action) return false;
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return microcycle == rhs.microcycle;
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}
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inline bool is_terminal() const {
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return action == Action::ScheduleNextProgram;
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}
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};
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/*!
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A micro-op is: (i) an action to take; and (ii) a sequence of bus operations
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to perform after taking the action.
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NOTE: this therefore has the opposite order of behaviour compared to a BusStep,
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the action occurs BEFORE the bus operations, not after.
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A nullptr bus_program terminates a sequence of micro operations; the is_terminal
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test should be used to query for that. The action on the final operation will
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be performed.
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*/
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struct MicroOp {
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enum class Action: int {
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None,
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/// Does whatever this instruction says is the main operation.
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PerformOperation,
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/// Sets the flags as if a MOVE operation had occurred, by inspecting *source.
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SetMoveFlagsb,
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SetMoveFlagsw,
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SetMoveFlagsl,
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/*
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All of the below will honour the source and destination masks
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in deciding where to apply their actions.
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*/
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/// Subtracts 1 from the [source/destination]_address.
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Decrement1,
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/// Subtracts 2 from the [source/destination]_address.
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Decrement2,
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/// Subtracts 4 from the [source/destination]_address.
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Decrement4,
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/// Adds 1 from the [source/destination]_address.
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Increment1,
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/// Adds 2 from the [source/destination]_address.
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Increment2,
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/// Adds 4 from the [source/destination]_address.
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Increment4,
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/// Copies the source and/or destination to effective_address_.
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CopyToEffectiveAddress,
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/// Peeking into the end of the prefetch queue, calculates the proper target of (d16,An) addressing.
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CalcD16An,
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/// Peeking into the end of the prefetch queue, calculates the proper target of (d8,An,Xn) addressing.
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CalcD8AnXn,
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/// Peeking into the prefetch queue, calculates the proper target of (d16,PC) addressing,
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/// adjusting as though it had been performed after the proper PC fetches. The source
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/// and destination mask flags affect only the destination of the result.
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CalcD16PC,
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/// Peeking into the prefetch queue, calculates the proper target of (d8,An,Xn) addressing,
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/// adjusting as though it had been performed after the proper PC fetches. The source
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/// and destination mask flags affect only the destination of the result.
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CalcD8PCXn,
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/// Sets the high word according to the MSB of the low word.
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SignExtendWord,
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/// Sets the high three bytes according to the MSB of the low byte.
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SignExtendByte,
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/// From the next word in the prefetch queue assembles a 0-padded 32-bit long word in either or
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/// both of effective_address_[0] and effective_address_[1].
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AssembleWordAddressFromPrefetch,
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/// From the next word in the prefetch queue assembles a 0-padded 32-bit long word in either or
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/// both of bus_data_[0] and bus_data_[1].
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AssembleWordDataFromPrefetch,
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/// Copies the next two prefetch words into one of the effective_address_.
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AssembleLongWordAddressFromPrefetch,
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/// Copies the next two prefetch words into one of the bus_data_.
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AssembleLongWordDataFromPrefetch,
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/// Copies the low part of the prefetch queue into next_word_.
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CopyNextWord,
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/// Performs write-back of post-increment address and/or sign extensions as necessary.
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MOVEMtoRComplete,
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/// Performs write-back of pre-decrement address.
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MOVEMtoMComplete,
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// (i) copies the current program counter to destination_bus_data_;
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// (ii) copies the stack pointer minus 2 to effective_address_[1];
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// (iii) decrements the stack pointer by four.
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PrepareJSR,
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// (i) copies the stack pointer to effective_address_[0];
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// (ii) increments the stack pointer by four.
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PrepareRTS,
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};
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static const int SourceMask = 1 << 30;
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static const int DestinationMask = 1 << 29;
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int action = int(Action::None);
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BusStep *bus_program = nullptr;
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MicroOp() {}
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MicroOp(int action) : action(action) {}
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MicroOp(int action, BusStep *bus_program) : action(action), bus_program(bus_program) {}
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MicroOp(Action action) : MicroOp(int(action)) {}
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MicroOp(Action action, BusStep *bus_program) : MicroOp(int(action), bus_program) {}
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inline bool is_terminal() const {
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return bus_program == nullptr;
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}
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};
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/*!
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A program represents the implementation of a particular opcode, as a sequence
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of micro-ops and, separately, the operation to perform plus whatever other
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fields the operation requires.
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*/
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struct Program {
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MicroOp *micro_operations = nullptr;
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RegisterPair32 *source = nullptr;
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RegisterPair32 *destination = nullptr;
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RegisterPair32 *source_address = nullptr;
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RegisterPair32 *destination_address = nullptr;
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Operation operation;
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bool requires_supervisor = false;
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void set_source(ProcessorStorage &storage, int mode, int reg) {
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source_address = &storage.address_[reg];
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switch(mode) {
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case 0: source = &storage.data_[reg]; break;
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case 1: source = &storage.address_[reg]; break;
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default: source = &storage.source_bus_data_[0]; break;
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}
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}
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void set_destination(ProcessorStorage &storage, int mode, int reg) {
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destination_address = &storage.address_[reg];
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switch(mode) {
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case 0: destination = &storage.data_[reg]; break;
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case 1: destination = &storage.address_[reg]; break;
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default: destination = &storage.destination_bus_data_[0]; break;
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}
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}
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};
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// Storage for all the sequences of bus steps and micro-ops used throughout
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// the 68000.
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std::vector<BusStep> all_bus_steps_;
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std::vector<MicroOp> all_micro_ops_;
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// A lookup table from instructions to implementations.
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Program instructions[65536];
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// Special steps for exception handlers.
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BusStep *reset_bus_steps_;
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// Special micro-op sequences and storage for conditionals.
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BusStep *branch_taken_bus_steps_;
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BusStep *branch_byte_not_taken_bus_steps_;
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BusStep *branch_word_not_taken_bus_steps_;
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uint32_t dbcc_false_address_;
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BusStep *dbcc_condition_true_steps_;
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BusStep *dbcc_condition_false_no_branch_steps_;
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BusStep *dbcc_condition_false_branch_steps_;
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BusStep *movem_reads_steps_;
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BusStep *movem_writes_steps_;
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// Current bus step pointer, and outer program pointer.
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Program *active_program_ = nullptr;
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MicroOp *active_micro_op_ = nullptr;
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BusStep *active_step_ = nullptr;
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uint16_t decoded_instruction_ = 0;
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uint16_t next_word_ = 0;
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/// Copies address_[7] to the proper stack pointer based on current mode.
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void write_back_stack_pointer();
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/// Sets or clears the supervisor flag, ensuring the stack pointer is properly updated.
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void set_is_supervisor(bool);
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// Transient storage for MOVEM.
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uint32_t movem_addresses_[65];
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RegisterPair16 movem_spare_value_;
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uint32_t movem_final_address_;
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/*!
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Evaluates the conditional described by @c code and returns @c true or @c false to
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indicate the result of that evaluation.
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*/
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inline bool evaluate_condition(uint8_t code) {
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switch(code & 0xf) {
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default:
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case 0x00: return true; // true
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case 0x01: return false; // false
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case 0x02: return zero_result_ && !carry_flag_; // high
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case 0x03: return !zero_result_ || carry_flag_; // low or same
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case 0x04: return !carry_flag_; // carry clear
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case 0x05: return carry_flag_; // carry set
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case 0x06: return zero_result_; // not equal
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case 0x07: return !zero_result_; // equal
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case 0x08: return !overflow_flag_; // overflow clear
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case 0x09: return overflow_flag_; // overflow set
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case 0x0a: return !negative_flag_; // positive
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case 0x0b: return negative_flag_; // negative
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case 0x0c: // greater than or equal
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return (negative_flag_ && overflow_flag_) || (!negative_flag_ && !overflow_flag_);
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case 0x0d: // less than
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return (negative_flag_ || !overflow_flag_) && (!negative_flag_ || overflow_flag_);
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case 0x0e: // greater than
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return zero_result_ && ((negative_flag_ && overflow_flag_) || (!negative_flag_ && !overflow_flag_));
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case 0x0f: // less than or equal
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return (!zero_result_ || negative_flag_) && (!overflow_flag_ || !negative_flag_) && overflow_flag_;
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}
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}
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private:
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friend class ProcessorStorageConstructor;
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};
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#endif /* MC68000Storage_h */
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