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159 lines
4.6 KiB
C++
159 lines
4.6 KiB
C++
//
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// 6850.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/10/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#include "6850.hpp"
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#define LOG_PREFIX "[6850] "
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#include "../../Outputs/Log.hpp"
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using namespace Motorola::ACIA;
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const HalfCycles ACIA::SameAsTransmit;
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ACIA::ACIA(HalfCycles transmit_clock_rate, HalfCycles receive_clock_rate) :
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transmit_clock_rate_(transmit_clock_rate),
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receive_clock_rate_((receive_clock_rate != SameAsTransmit) ? receive_clock_rate : transmit_clock_rate) {
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transmit.set_writer_clock_rate(transmit_clock_rate.as_int());
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request_to_send.set_writer_clock_rate(transmit_clock_rate.as_int());
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}
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uint8_t ACIA::read(int address) {
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if(address&1) {
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LOG("Read from receive register");
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interrupt_request_ = false;
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} else {
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LOG("Read status");
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return
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((next_transmission_ == NoTransmission) ? 0x02 : 0x00) |
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(data_carrier_detect.read() ? 0x04 : 0x00) |
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(clear_to_send.read() ? 0x08 : 0x00) |
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(interrupt_request_ ? 0x80 : 0x00)
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;
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// b0: receive data full.
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// b1: transmit data empty.
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// b2: DCD.
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// b3: CTS.
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// b4: framing error (i.e. no first stop bit where expected).
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// b5: receiver overran.
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// b6: parity error.
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// b7: IRQ state.
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}
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return 0x00;
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}
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void ACIA::write(int address, uint8_t value) {
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if(address&1) {
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next_transmission_ = value;
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consider_transmission();
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update_clocking_observer();
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interrupt_request_ = false;
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} else {
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if((value&3) == 3) {
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transmit.reset_writing();
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request_to_send.reset_writing();
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} else {
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switch(value & 3) {
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default:
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case 0: divider_ = 1; break;
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case 1: divider_ = 16; break;
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case 2: divider_ = 64; break;
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}
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switch((value >> 2) & 7) {
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default:
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case 0: data_bits_ = 7; stop_bits_ = 2; parity_ = Parity::Even; break;
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case 1: data_bits_ = 7; stop_bits_ = 2; parity_ = Parity::Odd; break;
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case 2: data_bits_ = 7; stop_bits_ = 1; parity_ = Parity::Even; break;
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case 3: data_bits_ = 7; stop_bits_ = 1; parity_ = Parity::Odd; break;
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case 4: data_bits_ = 8; stop_bits_ = 2; parity_ = Parity::None; break;
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case 5: data_bits_ = 8; stop_bits_ = 1; parity_ = Parity::None; break;
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case 6: data_bits_ = 8; stop_bits_ = 1; parity_ = Parity::Even; break;
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case 7: data_bits_ = 8; stop_bits_ = 1; parity_ = Parity::Odd; break;
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}
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switch((value >> 5) & 3) {
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case 0: request_to_send.write(false); transmit_interrupt_enabled_ = false; break;
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case 1: request_to_send.write(false); transmit_interrupt_enabled_ = true; break;
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case 2: request_to_send.write(true); transmit_interrupt_enabled_ = false; break;
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case 3:
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request_to_send.write(false);
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transmit_interrupt_enabled_ = false;
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transmit.reset_writing();
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transmit.write(false);
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break;
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}
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receive_interrupt_enabled_ = value & 0x80;
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}
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}
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}
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void ACIA::run_for(HalfCycles length) {
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// Transmission.
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const int transmit_advance = length.as_int();
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const auto write_data_time_remaining = transmit.write_data_time_remaining();
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if(write_data_time_remaining) {
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if(transmit_advance > write_data_time_remaining) {
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if(next_transmission_ != NoTransmission) {
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transmit.flush_writing();
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consider_transmission();
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transmit.advance_writer(transmit_advance - write_data_time_remaining);
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} else {
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transmit.advance_writer(transmit_advance);
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update_clocking_observer();
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interrupt_request_ |= transmit_interrupt_enabled_;
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}
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} else {
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transmit.advance_writer(transmit_advance);
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}
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}
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// Reception.
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}
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void ACIA::consider_transmission() {
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if(next_transmission_ != NoTransmission && !transmit.write_data_time_remaining()) {
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// Establish start bit and [7 or 8] data bits.
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if(data_bits_ == 7) next_transmission_ &= 0x7f;
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int transmission = next_transmission_ << 1;
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// Add a parity bit, if any.
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int mask = 0x2 << data_bits_;
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if(parity_ != Parity::None) {
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next_transmission_ ^= next_transmission_ >> 4;
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next_transmission_ ^= next_transmission_ >> 2;
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next_transmission_ ^= next_transmission_ >> 1;
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if((next_transmission_&1) != (parity_ == Parity::Even)) {
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transmission |= mask;
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}
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mask <<= 1;
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}
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// Add stop bits.
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for(int c = 0; c < stop_bits_; ++c) {
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transmission |= mask;
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mask <<= 1;
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}
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// Output all that.
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const int total_bits = 1 + data_bits_ + stop_bits_ + (parity_ != Parity::None);
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transmit.write(divider_, total_bits, transmission);
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// Mark the transmit register as empty again.
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next_transmission_ = NoTransmission;
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}
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}
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ClockingHint::Preference ACIA::preferred_clocking() {
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return (transmit.write_data_time_remaining() > 0) ? ClockingHint::Preference::JustInTime : ClockingHint::Preference::None;
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}
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bool ACIA::get_interrupt_line() const {
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return interrupt_request_;
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}
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