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297 lines
8.8 KiB
C++
297 lines
8.8 KiB
C++
//
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// Macintosh.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 03/05/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#include "Macintosh.hpp"
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#include <array>
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#include "Video.hpp"
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#include "../../CRTMachine.hpp"
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#include "../../../Processors/68000/68000.hpp"
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#include "../../../Components/6522/6522.hpp"
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#include "../../../Components/DiskII/IWM.hpp"
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#include "../../Utility/MemoryPacker.hpp"
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namespace Apple {
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namespace Macintosh {
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class ConcreteMachine:
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public Machine,
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public CRTMachine::Machine,
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public CPU::MC68000::BusHandler {
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public:
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ConcreteMachine(const ROMMachine::ROMFetcher &rom_fetcher) :
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mc68000_(*this),
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video_(ram_.data()),
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via_(via_port_handler_),
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via_port_handler_(*this),
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iwm_(7833600) {
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// Grab a copy of the ROM and convert it into big-endian data.
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const auto roms = rom_fetcher("Macintosh", { "mac128k.rom" });
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if(!roms[0]) {
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throw ROMMachine::Error::MissingROMs;
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}
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roms[0]->resize(64*1024);
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Memory::PackBigEndian16(*roms[0], rom_.data());
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// The Mac runs at 7.8336mHz.
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set_clock_rate(7833600.0);
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}
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void set_scan_target(Outputs::Display::ScanTarget *scan_target) override {
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video_.set_scan_target(scan_target);
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}
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Outputs::Speaker::Speaker *get_speaker() override {
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return nullptr;
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}
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void run_for(const Cycles cycles) override {
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mc68000_.run_for(cycles);
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}
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using Microcycle = CPU::MC68000::Microcycle;
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HalfCycles perform_bus_operation(const Microcycle &cycle, int is_supervisor) {
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time_since_video_update_ += cycle.length;
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time_since_iwm_update_ += cycle.length;
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// Assumption here: it's a divide by ten to derive the 6522 clock, i.e.
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// it runs off the 68000's E clock.
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via_clock_ += cycle.length;
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via_.run_for(via_clock_.divide(HalfCycles(10)));
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// SCC is a divide-by-two.
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// A null cycle leaves nothing else to do.
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if(cycle.operation) {
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auto word_address = cycle.word_address();
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// The 6522 is accessed via the synchronous bus.
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mc68000_.set_is_peripheral_address((word_address & 0x7ff0ff) == 0x77f0ff);
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if(word_address >= 0x400000) {
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if(cycle.data_select_active()) {
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// printf("IO access to %06x: ", word_address << 1);
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const int register_address = word_address >> 8;
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switch(word_address & 0x78f000) {
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case 0x70f000:
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// VIA accesses are via address 0xefe1fe + register*512,
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// which at word precision is 0x77f0ff + register*256.
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = via_.get_register(register_address);
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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} else {
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via_.set_register(register_address, cycle.value->halves.low);
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}
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break;
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case 0x68f000:
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// The IWM; this is a purely polled device, so can be run on demand.
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iwm_.run_for(time_since_iwm_update_.flush_cycles());
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = iwm_.read(register_address);
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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} else {
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iwm_.write(register_address, cycle.value->halves.low);
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}
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// printf("IWM %d %c [%02x]\n", register_address & 0xf, (cycle.operation & Microcycle::Read) ? 'r' : 'w', cycle.value->halves.low);
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break;
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default:
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printf("Unrecognised %c [%06x]\n", (cycle.operation & Microcycle::Read) ? 'r' : 'w', *cycle.address & 0xffffff);
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = 0xff;
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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}
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break;
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}
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}
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} else {
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if(cycle.data_select_active()) {
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uint16_t *memory_base = nullptr;
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// When ROM overlay is enabled, the ROM begins at both $000000 and $400000,
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// and RAM is available at $600000.
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//
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// Otherwise RAM is mapped at $000000 and ROM from $400000.
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//
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// Writes to the RAM area, at least, seem to go to RAM regardless of the ROM
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// overlay setting, so for now I'm gambling below that writes just always go to RAM.
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if(
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!(cycle.operation & Microcycle::Read) ||
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(
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(ROM_is_overlay_ && word_address >= 0x300000) ||
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(!ROM_is_overlay_ && !(word_address & 0x200000))
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)
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) {
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memory_base = ram_.data();
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word_address %= ram_.size();
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} else {
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memory_base = rom_.data();
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word_address %= rom_.size();
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}
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge)) {
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default: break;
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = memory_base[word_address];
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// printf("[%06x] -> %04x\n", word_address << 1, cycle.value->full);
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = uint8_t(memory_base[word_address] >> cycle.byte_shift());
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// printf("[%06x] -> %02x\n", (*cycle.address) & 0xffffff, cycle.value->halves.low);
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break;
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case Microcycle::SelectWord:
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// printf("%04x -> [%06x]\n", cycle.value->full, word_address << 1);
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memory_base[word_address] = cycle.value->full;
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break;
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case Microcycle::SelectByte:
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// printf("%02x -> [%06x]\n", cycle.value->halves.low, (*cycle.address) & 0xffffff);
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memory_base[word_address] = uint16_t(
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(cycle.value->halves.low << cycle.byte_shift()) |
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(memory_base[word_address] & cycle.untouched_byte_mask())
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);
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break;
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}
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} else {
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// TODO: add delay if this is a RAM access and video blocks it momentarily.
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// "Each [video] fetch took two cycles out of eight"
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}
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}
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}
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/*
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Normal memory map:
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000000: RAM
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400000: ROM
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9FFFF8+: SCC read operations
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BFFFF8+: SCC write operations
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DFE1FF+: IWM
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EFE1FE+: VIA
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*/
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return HalfCycles(0);
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}
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void flush() {
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video_.run_for(time_since_video_update_.flush());
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}
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void set_rom_is_overlay(bool rom_is_overlay) {
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ROM_is_overlay_ = rom_is_overlay;
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}
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void set_use_alternate_screen_buffer(bool use_alternate_screen_buffer) {
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video_.set_use_alternate_screen_buffer(use_alternate_screen_buffer);
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}
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private:
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class VIAPortHandler: public MOS::MOS6522::PortHandler {
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public:
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VIAPortHandler(ConcreteMachine &machine) : machine_(machine) {}
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using Port = MOS::MOS6522::Port;
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using Line = MOS::MOS6522::Line;
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void set_port_output(Port port, uint8_t value, uint8_t direction_mask) {
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/*
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Peripheral lines: keyboard data, interrupt configuration.
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(See p176 [/215])
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*/
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switch(port) {
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case Port::A:
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/*
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Port A:
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b7: [input] SCC wait/request (/W/REQA and /W/REQB wired together for a logical OR)
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b6: 0 = alternate screen buffer, 1 = main screen buffer
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b5: floppy disk SEL state control (upper/lower head "among other things")
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b4: 1 = use ROM overlay memory map, 0 = use ordinary memory map
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b3: 0 = use alternate sound buffer, 1 = use ordinary sound buffer
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b2–b0: audio output volume
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*/
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// printf("6522 A: %02x\n", value);
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machine_.set_rom_is_overlay(!!(value & 0x10));
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machine_.set_use_alternate_screen_buffer(!(value & 0x40));
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break;
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case Port::B:
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/*
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Port B:
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b7: 0 = sound enabled, 1 = sound disabled
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b6: [input] 0 = video beam in visible portion of line, 1 = outside
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b5: [input] mouse y2
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b4: [input] mouse x2
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b3: [input] 0 = mouse button down, 1 = up
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b2: 0 = real-time clock enabled, 1 = disabled
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b1: clock's data-clock line
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b0: clock's serial data line
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*/
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// printf("6522 B: %02x\n", value);
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break;
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}
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}
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uint8_t get_port_input(Port port) {
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switch(port) {
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case Port::A:
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// printf("6522 r A\n");
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return 0xff;
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case Port::B:
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// printf("6522 r B\n");
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return 0x00;
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}
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}
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void set_control_line_output(Port port, Line line, bool value) {
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// printf("6522 line %c%d: %c\n", port ? 'B' : 'A', int(line), value ? 't' : 'f');
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}
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private:
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ConcreteMachine &machine_;
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};
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std::array<uint16_t, 32*1024> rom_;
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std::array<uint16_t, 64*1024> ram_;
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CPU::MC68000::Processor<ConcreteMachine, true> mc68000_;
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Video video_;
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MOS::MOS6522::MOS6522<VIAPortHandler> via_;
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VIAPortHandler via_port_handler_;
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Apple::IWM iwm_;
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HalfCycles via_clock_;
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HalfCycles time_since_video_update_;
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HalfCycles time_since_iwm_update_;
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bool ROM_is_overlay_ = true;
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};
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}
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}
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using namespace Apple::Macintosh;
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Machine *Machine::Macintosh(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
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return new ConcreteMachine(rom_fetcher);
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}
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Machine::~Machine() {}
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