1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-23 03:32:32 +00:00
CLK/OSBindings/Mac/Clock SignalTests
2017-07-27 21:19:16 -04:00
..
AllSuiteA
Atari ROMs
BCDTest
Bridges Corrected timestamp return, and its testing by the 6502 timing tests. 2017-07-27 21:19:16 -04:00
FUSE
Klaus Dormann
Wolfgang Lorenz 6502 test suite
Zexall
6502InterruptTests.swift
6502TimingTests.swift Corrected timestamp return, and its testing by the 6502 timing tests. 2017-07-27 21:19:16 -04:00
6522Tests.swift
6532Tests.swift
AllSuiteATests.swift
ArrayBuilderTests.mm
AtariStaticAnalyserTests.mm
BCDTest.swift Completed fixture of the 6502 BCD test. 2017-07-25 22:55:45 -04:00
C1540Tests.swift
CRCTests.mm
DPLLTests.swift Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests. 2017-07-16 20:55:57 -04:00
FUSETests.swift Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests. 2017-07-27 20:17:13 -04:00
Info.plist
KlausDormannTests.swift
PCMPatchedTrackTests.mm
PCMSegmentEventSourceTests.mm
PCMTrackTests.mm
TIATests.mm The TIA is now a ClockReceiver. 2017-07-24 21:48:34 -04:00
TimeTests.mm
WolfgangLorenzTests.swift
Z80InterruptTests.swift
Z80MachineCycleTests.swift Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests. 2017-07-27 20:17:13 -04:00
Z80MemptrTests.swift Added test for 16-bit arithmetic, and fixed implementation. 2017-07-26 19:04:52 -04:00
ZexallTests.swift