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522 lines
12 KiB
C++
522 lines
12 KiB
C++
//
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// Audio.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 09/11/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#include "Audio.hpp"
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#include "Flags.hpp"
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#define LOG_PREFIX "[Audio] "
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#include "../../Outputs/Log.hpp"
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#include <cassert>
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using namespace Amiga;
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Audio::Audio(Chipset &chipset, uint16_t *ram, size_t word_size, float output_rate) :
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DMADevice<4>(chipset, ram, word_size) {
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// Mark all buffers as available.
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for(auto &flag: buffer_available_) {
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flag.store(true, std::memory_order::memory_order_relaxed);
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}
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speaker_.set_input_rate(output_rate);
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}
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bool Audio::advance_dma(int channel) {
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if(channels_[channel].has_data) {
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return false;
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}
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set_data(channel, ram_[pointer_[size_t(channel)]]);
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if(channels_[channel].state != Channel::State::WaitingForDummyDMA) {
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++pointer_[size_t(channel)];
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}
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return true;
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}
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void Audio::set_length(int channel, uint16_t length) {
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assert(channel >= 0 && channel < 4);
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channels_[channel].length = length;
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}
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void Audio::set_period(int channel, uint16_t period) {
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assert(channel >= 0 && channel < 4);
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channels_[channel].period = period;
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}
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void Audio::set_volume(int channel, uint16_t volume) {
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assert(channel >= 0 && channel < 4);
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channels_[channel].volume = (volume & 0x40) ? 64 : (volume & 0x3f);
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}
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void Audio::set_data(int channel, uint16_t data) {
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assert(channel >= 0 && channel < 4);
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channels_[channel].has_data = true;
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channels_[channel].data = data;
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}
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void Audio::set_channel_enables(uint16_t enables) {
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channels_[0].dma_enabled = enables & 1;
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channels_[1].dma_enabled = enables & 2;
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channels_[2].dma_enabled = enables & 4;
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channels_[3].dma_enabled = enables & 8;
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}
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void Audio::set_modulation_flags(uint16_t) {
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}
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void Audio::set_interrupt_requests(uint16_t requests) {
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channels_[0].interrupt_pending = requests & uint16_t(InterruptFlag::AudioChannel0);
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channels_[1].interrupt_pending = requests & uint16_t(InterruptFlag::AudioChannel1);
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channels_[2].interrupt_pending = requests & uint16_t(InterruptFlag::AudioChannel2);
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channels_[3].interrupt_pending = requests & uint16_t(InterruptFlag::AudioChannel3);
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}
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void Audio::output() {
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constexpr InterruptFlag interrupts[] = {
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InterruptFlag::AudioChannel0,
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InterruptFlag::AudioChannel1,
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InterruptFlag::AudioChannel2,
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InterruptFlag::AudioChannel3,
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};
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for(int c = 0; c < 4; c++) {
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if(channels_[c].output()) {
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posit_interrupt(interrupts[c]);
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}
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}
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// TEMPORARY: just fill the audio buffer with silence.
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if(!sample_pointer_) {
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while(!buffer_available_[buffer_pointer_].load(std::memory_order::memory_order_relaxed));
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}
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buffer_[buffer_pointer_][sample_pointer_] = int16_t(
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(
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int8_t(channels_[0].output_level) * channels_[0].output_enabled +
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int8_t(channels_[2].output_level) * channels_[2].output_enabled
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) << 7
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);
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buffer_[buffer_pointer_][sample_pointer_+1] = int16_t(
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(
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int8_t(channels_[1].output_level) * channels_[1].output_enabled +
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int8_t(channels_[3].output_level) * channels_[3].output_enabled
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) << 7
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);
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sample_pointer_ += 2;
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if(sample_pointer_ == buffer_[buffer_pointer_].size()) {
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const auto &buffer = buffer_[buffer_pointer_];
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auto &flag = buffer_available_[buffer_pointer_];
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flag.store(false, std::memory_order::memory_order_release);
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queue_.enqueue([this, &buffer, &flag] {
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speaker_.push(buffer.data(), buffer.size() >> 1);
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flag.store(true, std::memory_order::memory_order_relaxed);
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});
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buffer_pointer_ = (buffer_pointer_ + 1) % BufferCount;
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sample_pointer_ = 0;
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}
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}
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/*
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Big spiel on the state machine:
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Commodore's Hardware Rerefence Manual provides the audio subsystem's state
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machine, so I've just tried to reimplement it verbatim. It's depicted
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diagrammatically in the original source as a finite state automata, the
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below is my attempt to translate that into text.
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000 State::Disabled:
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-> State::Disabled (000)
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if: N/A
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action: percntrld
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-> State::PlayingHigh (010)
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if: AUDDAT, and not AUDxON, and not AUDxIP
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action: volcntrld, percntrld, pbudld1, AUDxIR
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-> State::WaitingForDummyDMA (001)
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if: AUDxON
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action: lencntrld, AUDxDR, dmasen*, percntrld
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* NOTE: except for this case, dmasen is true only when
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LENFIN = 1. Also, AUDxDSR = (AUDxDR and dmasen).
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001 State::WaitingForDummyDMA:
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-> State::WaitingForDummyDMA (001)
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if: N/A
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action: None
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-> State::Disabled (000)
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if: not AUDxON
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action: None
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-> State::WaitingForDMA (101)
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if: AUDxON, and AUDxDAT
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action:
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1. AUDxIR
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2. if not lenfin, then lencount
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101 State::WaitingForDMA:
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-> State::WaitingForDMA (101)
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if: N/A
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action: None
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-> State:Disabled (000)
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if: not AUDxON
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action: None
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-> State::PlayingHigh (010)
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if: AUDxON, and AUDxDAT
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action:
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1. volcntrld, percntrld, pbufid1
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2. if napnav, then AUDxDR
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010 State::PlayingHigh
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-> State::PlayingHigh (010)
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if: N/A
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action: percount, and penhi
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-> State::PlayingLow (011)
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if: perfin
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action:
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1. if AUDxAP, then pubfid2
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2. if AUDxAP and AUDxON, then AUDxDR
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3. percntrld
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4. if intreq2 and AUDxON and AUDxAP, then AUDxIR
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5. if AUDxAP and AUDxON, then AUDxIR
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6. if lenfin and AUDxON and AUDxDAT, then lencntrld
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7. if (not lenfin) and AUDxON and AUDxDAT, then lencount
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8. if lenfin and AUDxON and AUDxDAT, then intreq2
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[note that 6–8 are shared with the Low -> High transition]
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011 State::PlayingLow
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-> State::PlayingLow (011)
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if: N/A
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action: percount, and not penhi
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-> State::Disabled (000)
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if: perfin and not (AUDxON and not AUDxIP)
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action: None
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-> State::PlayingHigh (010)
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if: perfin and AUDxON and not AUDxIP
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action:
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1. pbufld
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2. percntrld
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3. if AUDxON and napnav, then AUDxDR
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4. if intreq2 and napnav and AUDxON, AUDxIR
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5. if napnav and not AUDxON, AUDxIR
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6. if lenfin and AUDxON and AUDxDAT, then lencntrld
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7. if (not lenfin) and AUDxON and AUDxDAT, then lencount
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8. if lenfin and AUDxON and AUDxDAT, then intreq2
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[note that 6-8 are shared with the High -> Low transition]
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Definitions:
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AUDxON DMA on "x" indicates channel number (signal from DMACON).
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AUDxIP Audio interrupt pending (input to channel from interrupt circuitry).
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AUDxIR Audio interrupt request (output from channel to interrupt circuitry)
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intreq1 Interrupt request that combines with intreq2 to form AUDxIR.
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intreq2 Prepare for interrupt request. Request comes out after the
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next 011->010 transition in normal operation.
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AUDxDAT Audio data load signal. Loads 16 bits of data to audio channel.
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AUDxDR Audio DMA request to Agnus for one word of data.
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AUDxDSR Audio DMA request to Agnus to reset pointer to start of block.
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dmasen Restart request enable.
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percntrld Reload period counter from back-up latch typically written
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by processor with AUDxPER (can also be written by attach mode).
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percount Count period counter down one latch.
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perfin Period counter finished (value = 1).
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lencntrld Reload length counter from back-up latch.
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lencount Count length counter down one notch.
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lenfin Length counter finished (value = 1).
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volcntrld Reload volume counter from back-up latch.
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pbufld1 Load output buffer from holding latch written to by AUDxDAT.
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pbufld2 Like pbufld1, but only during 010->011 with attach period.
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AUDxAV Attach volume. Send data to volume latch of next channel
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instead of to D->A converter.
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AUDxAP Attach period. Send data to period latch of next channel
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instead of to the D->A converter.
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penhi Enable the high 8 bits of data to go to the D->A converter.
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napnav /AUDxAV * /AUDxAP + AUDxAV -- no attach stuff or else attach
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volume. Condition for normal DMA and interrupt requests.
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*/
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//
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// Non-action fallback transition.
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//
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template <
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Audio::Channel::State begin,
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Audio::Channel::State end> bool Audio::Channel::transit() {
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state = end;
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return false;
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}
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//
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// Audio::Channel::State::Disabled
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//
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template <> bool Audio::Channel::transit<
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Audio::Channel::State::Disabled,
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Audio::Channel::State::WaitingForDummyDMA>() {
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state = State::WaitingForDummyDMA;
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period_counter = period; // i.e. percntrld
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length_counter = length; // i.e. lencntrld
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return false;
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}
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template <> bool Audio::Channel::transit<
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Audio::Channel::State::Disabled,
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Audio::Channel::State::PlayingHigh>() {
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state = State::PlayingHigh;
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data_latch = data; // i.e. pbufld1
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has_data = false;
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period_counter = period; // i.e. percntrld
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// TODO: volcntrld (see above).
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// Request an interrupt.
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return true;
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}
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template <> bool Audio::Channel::output<Audio::Channel::State::Disabled>() {
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if(has_data && !dma_enabled && !interrupt_pending) {
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return transit<State::Disabled, State::PlayingHigh>();
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}
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// Test for DMA-style transition.
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if(dma_enabled) {
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return transit<State::Disabled, State::WaitingForDummyDMA>();
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}
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return false;
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}
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//
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// Audio::Channel::State::WaitingForDummyDMA
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//
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template <> bool Audio::Channel::transit<
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Audio::Channel::State::WaitingForDummyDMA,
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Audio::Channel::State::WaitingForDMA>() {
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state = State::WaitingForDMA;
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has_data = false;
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if(length == 1) {
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length_counter = length;
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return true;
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}
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return false;
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}
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template <> bool Audio::Channel::output<Audio::Channel::State::WaitingForDummyDMA>() {
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if(!dma_enabled) {
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return transit<State::WaitingForDummyDMA, State::Disabled>();
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}
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if(dma_enabled && has_data) {
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return transit<State::WaitingForDummyDMA, State::WaitingForDMA>();
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}
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return false;
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}
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//
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// Audio::Channel::State::WaitingForDMA
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//
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template <> bool Audio::Channel::transit<
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Audio::Channel::State::WaitingForDMA,
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Audio::Channel::State::PlayingHigh>() {
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state = State::PlayingHigh;
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data_latch = data;
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has_data = false;
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period_counter = period; // i.e. percntrld
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return false;
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}
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template <> bool Audio::Channel::output<Audio::Channel::State::WaitingForDMA>() {
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if(!dma_enabled) {
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return transit<State::WaitingForDummyDMA, State::Disabled>();
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}
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if(dma_enabled && has_data) {
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return transit<State::WaitingForDummyDMA, State::PlayingHigh>();
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}
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return false;
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}
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//
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// Audio::Channel::State::PlayingHigh
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//
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template <> bool Audio::Channel::transit<
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Audio::Channel::State::PlayingHigh,
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Audio::Channel::State::PlayingLow>() {
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state = State::PlayingLow;
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// TODO: if AUDxAP, then pubfid2
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// TODO: if AUDxAP and AUDxON, then AUDxDR
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period_counter = period; // i.e. percntrld
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// TODO: if intreq2 and AUDxON and AUDxAP, then AUDxIR
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// TODO: if AUDxAP and AUDxON, then AUDxIR
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// if lenfin and AUDxON and AUDxDAT, then lencntrld
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// if (not lenfin) and AUDxON and AUDxDAT, then lencount
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// if lenfin and AUDxON and AUDxDAT, then intreq2
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if(dma_enabled && has_data) {
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--length_counter;
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if(!length_counter) {
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length_counter = length;
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will_request_interrupt = true;
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}
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}
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return false;
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}
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template <> bool Audio::Channel::output<Audio::Channel::State::PlayingHigh>() {
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-- period_counter;
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// This is a reasonable guess as to the exit condition for this node;
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// Commodore doesn't document.
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if(!period_counter) {
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return transit<State::PlayingHigh, State::PlayingLow>();
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}
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// Output high byte.
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output_level = data_latch >> 8;
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return false;
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}
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//
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// Audio::Channel::State::PlayingLow
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//
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template <> bool Audio::Channel::transit<
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Audio::Channel::State::PlayingLow,
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Audio::Channel::State::PlayingHigh>() {
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state = State::PlayingHigh;
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// TODO: include napnav in tests
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if(!dma_enabled) {
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return true;
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} else {
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data_latch = data; // i.e. pbufld2
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has_data = false; // AUDxDR
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}
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if(dma_enabled && will_request_interrupt) {
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will_request_interrupt = false;
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return true;
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}
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return false;
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}
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template <> bool Audio::Channel::output<Audio::Channel::State::PlayingLow>() {
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-- period_counter;
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const bool dma_and_not_done = dma_enabled && !interrupt_pending;
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if(!period_counter && !dma_and_not_done) {
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return transit<State::PlayingLow, State::Disabled>();
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}
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if(!period_counter && dma_and_not_done) {
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return transit<State::PlayingLow, State::PlayingHigh>();
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}
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// Output low byte.
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output_level = data_latch & 0xff;
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return false;
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}
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//
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// Dispatcher
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//
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bool Audio::Channel::output() {
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// Update pulse-width modulation.
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output_phase = (output_phase + 1) & 63;
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output_enabled |= !output_phase;
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output_enabled &= output_phase != volume;
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switch(state) {
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case State::Disabled: return output<State::Disabled>();
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case State::WaitingForDummyDMA: return output<State::WaitingForDummyDMA>();
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case State::WaitingForDMA: return output<State::WaitingForDMA>();
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case State::PlayingHigh: return output<State::PlayingHigh>();
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case State::PlayingLow: return output<State::PlayingLow>();
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default:
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assert(false);
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break;
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}
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return false;
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}
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