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CLK
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CLK
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OSBindings
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Mac
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Clock SignalTests
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Bridges
History
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
..
C1540Bridge.h
…
C1540Bridge.mm
…
Clock SignalTests-Bridging-Header.h
…
DigitalPhaseLockedLoopBridge.h
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DigitalPhaseLockedLoopBridge.mm
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MOS6522Bridge.h
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MOS6522Bridge.mm
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MOS6532Bridge.h
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MOS6532Bridge.mm
…
TestMachine6502.h
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
TestMachine6502.mm
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
TestMachine.h
…
TestMachine.mm
Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
2017-06-03 21:22:16 -04:00
TestMachine+ForSubclassEyesOnly.h
…
TestMachineZ80.h
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TestMachineZ80.mm
…