Thomas Harte 98751e6ac8 Ensures that all result phases are exactly the intended length by replacing accumulation with assignment. ...

Also attempts a different version of control mark behaviour. Experiments.

2017-09-15 22:59:26 -04:00

..

1770

Puts the disk controller back into the loop with knowledge about reading mode, and uses that knowledge to cut off the PLL.

2017-09-14 22:30:40 -04:00

6522

Explicitly disallows copying of VIAs, and marks the constructor as noexcept.

2017-09-05 21:21:23 -04:00

6532

Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.

2017-07-27 22:05:29 -04:00

6560

Corrects the US colour palette, effectively undoing what was a mistaken adjustment for the time when Oric-centric phase alignment was built into the CRT based on a false calculation that it wouldn't affect the machines that generate chrominance functionally.

2017-08-16 09:58:34 -04:00

6845

Adds an initial implementation of display skew, as a completely live property.

2017-08-29 22:16:40 -04:00

8255

Improved comments.

2017-08-08 07:44:46 -04:00

8272

Ensures that all result phases are exactly the intended length by replacing accumulation with assignment.

2017-09-15 22:59:26 -04:00

AY38910

Inverted meaning of register_masks, as it's a bit weird that the mask is inverted immediately upon usage. It's a left-over from thinking the unused bits should be 1s; unit tests reveal they should be 0s. Comment updated appropriately.

2017-08-16 09:29:48 -04:00