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CLK
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988bbb5ab1
CLK
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Machines
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Oric
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Thomas Harte
988bbb5ab1
Ensured AY registers aren't rewritten just because of a synchronise event. A stall prior to figuring out proper bus logic, clearly.
2016-10-17 08:05:57 -04:00
..
Oric.cpp
Performed enough wiring to put the onus back onto OricTAP to do appropriate things.
2016-10-15 21:32:59 -04:00
Oric.hpp
Ensured AY registers aren't rewritten just because of a synchronise event. A stall prior to figuring out proper bus logic, clearly.
2016-10-17 08:05:57 -04:00
Video.cpp
Altered phase so that it now merely accounts for accumulated error across a frame. Can probably do better.
2016-10-17 08:04:15 -04:00
Video.hpp
Fixed inverse characters, added an extra per-frame phase change, based on empirical observation, ensured header guard won't become ambiguous.
2016-10-16 22:14:01 -04:00