Thomas Harte 9c43776392 Fix 80-column address generation.		2023-02-14 21:14:35 -05:00
..
1770
5380	Continue DMA requests if writing, even after a phase mismatch.	2022-09-15 16:46:22 -04:00
6522
6526	Avoid unnecessary get_port_input calls.	2021-11-24 17:15:48 -05:00
6532
6560	Switch name back to emphasise _async_.	2022-07-16 14:41:04 -04:00
6845
6850	Introduce the principle that a Serial::Line can be two-wire — clock + data.	2021-11-06 16:54:20 -07:00
8255
8272	Adds a Qt timer class. Precision seems to be 'acceptable'.	2020-05-31 23:39:08 -04:00
8530	Ensures no double definition of NDEBUG.	2021-03-07 12:52:54 -05:00
9918	Fix 80-column address generation.	2023-02-14 21:14:35 -05:00
68901	Fix include order.	2023-01-14 14:16:56 -05:00
AppleClock
AudioToggle	Switch name back to emphasise _async_.	2022-07-16 14:41:04 -04:00
AY38910	Switch name back to emphasise _async_.	2022-07-16 14:41:04 -04:00
DiskII
KonamiSCC	Switch name back to emphasise _async_.	2022-07-16 14:41:04 -04:00
OPx	Switch name back to emphasise _async_.	2022-07-16 14:41:04 -04:00
RP5C01	Months seem to start at 1; also fix seeded year for MSX.	2023-01-23 22:52:26 -05:00
Serial	Add header for assert.	2021-11-24 16:28:18 -05:00
SN76489	Switch name back to emphasise _async_.	2022-07-16 14:41:04 -04:00