mirror of
https://github.com/TomHarte/CLK.git
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534 lines
21 KiB
C++
534 lines
21 KiB
C++
//
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//
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// PerformImplementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 05/10/2023.
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// Copyright © 2023 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "Arithmetic.hpp"
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#include "BCD.hpp"
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#include "FlowControl.hpp"
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#include "InOut.hpp"
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#include "LoadStore.hpp"
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#include "Logical.hpp"
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#include "Repetition.hpp"
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#include "Resolver.hpp"
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#include "ShiftRoll.hpp"
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#include "Stack.hpp"
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#include "../Interrupts.hpp"
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#include "../AccessType.hpp"
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//
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// Comments throughout headers above come from the 1997 edition of the
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// Intel Architecture Software Developer’s Manual; that year all such
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// definitions still fitted within a single volume, Volume 2.
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//
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// Order Number 243191; e.g. https://www.ardent-tool.com/CPU/docs/Intel/IA/243191-002.pdf
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//
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namespace InstructionSet::x86 {
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template <
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DataSize data_size,
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AddressSize address_size,
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typename InstructionT,
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typename ContextT
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> void perform(
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const InstructionT &instruction,
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ContextT &context
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) {
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using IntT = typename DataSizeType<data_size>::type;
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using AddressT = typename AddressSizeType<address_size>::type;
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// Establish source() and destination() shorthands to fetch data if necessary.
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//
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// C++17, which this project targets at the time of writing, does not provide templatised lambdas.
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// So the following division is in part a necessity.
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//
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// (though GCC offers C++20 syntax as an extension, and Clang seems to follow along, so maybe I'm overthinking)
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IntT immediate;
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const auto source_r = [&]() -> read_t<IntT> {
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return resolve<IntT, AccessType::Read>(
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instruction,
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instruction.source().source(),
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instruction.source(),
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context,
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nullptr,
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&immediate);
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};
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const auto source_rmw = [&]() -> modify_t<IntT> {
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return resolve<IntT, AccessType::ReadModifyWrite>(
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instruction,
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instruction.source().source(),
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instruction.source(),
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context,
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nullptr,
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&immediate);
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};
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const auto destination_r = [&]() -> read_t<IntT> {
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return resolve<IntT, AccessType::Read>(
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instruction,
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instruction.destination().source(),
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instruction.destination(),
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context,
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nullptr,
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&immediate);
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};
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const auto destination_w = [&]() -> write_t<IntT> {
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return resolve<IntT, AccessType::Write>(
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instruction,
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instruction.destination().source(),
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instruction.destination(),
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context,
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nullptr,
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&immediate);
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};
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const auto destination_rmw = [&]() -> modify_t<IntT> {
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return resolve<IntT, AccessType::ReadModifyWrite>(
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instruction,
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instruction.destination().source(),
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instruction.destination(),
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context,
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nullptr,
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&immediate);
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};
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// Performs a displacement jump only if @c condition is true.
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const auto jcc = [&](bool condition) {
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Primitive::jump(
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condition,
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instruction.displacement(),
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context);
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};
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const auto shift_count = [&]() -> uint8_t {
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static constexpr uint8_t mask = (ContextT::model != Model::i8086) ? 0x1f : 0xff;
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switch(instruction.source().source()) {
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case Source::None: return 1;
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case Source::Immediate: return uint8_t(instruction.operand()) & mask;
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default: return context.registers.cl() & mask;
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}
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};
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// Some instructions use a pair of registers as an extended accumulator — DX:AX or EDX:EAX.
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// The two following return the high and low parts of that pair; they also work in Byte mode to return AH:AL,
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// i.e. AX split into high and low parts.
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const auto pair_high = [&]() -> IntT& {
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if constexpr (data_size == DataSize::Byte) return context.registers.ah();
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else if constexpr (data_size == DataSize::Word) return context.registers.dx();
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else if constexpr (data_size == DataSize::DWord) return context.registers.edx();
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};
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const auto pair_low = [&]() -> IntT& {
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if constexpr (data_size == DataSize::Byte) return context.registers.al();
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else if constexpr (data_size == DataSize::Word) return context.registers.ax();
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else if constexpr (data_size == DataSize::DWord) return context.registers.eax();
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};
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// For the string operations, evaluate to either SI and DI or ESI and EDI, depending on the address size.
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const auto eSI = [&]() -> AddressT& {
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if constexpr (std::is_same_v<AddressT, uint16_t>) {
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return context.registers.si();
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} else {
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return context.registers.esi();
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}
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};
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const auto eDI = [&]() -> AddressT& {
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if constexpr (std::is_same_v<AddressT, uint16_t>) {
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return context.registers.di();
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} else {
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return context.registers.edi();
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}
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};
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// For counts, provide either eCX or CX depending on address size.
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const auto eCX = [&]() -> AddressT& {
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if constexpr (std::is_same_v<AddressT, uint16_t>) {
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return context.registers.cx();
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} else {
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return context.registers.ecx();
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}
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};
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// Gets the port for an IN or OUT; these are always 16-bit.
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const auto port = [&](Source source) -> uint16_t {
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switch(source) {
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case Source::DirectAddress: return instruction.offset();
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default: return context.registers.dx();
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}
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};
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// Guide to the below:
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//
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// * use hard-coded register names where appropriate, otherwise use the source_X() and destination_X() lambdas;
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// * return directly if there is definitely no possible write back to RAM;
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// * break if there's a chance of writeback.
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switch(instruction.operation()) {
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default:
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assert(false);
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case Operation::Invalid:
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// TODO: throw on higher-order processors.
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case Operation::ESC:
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case Operation::NOP: return;
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case Operation::AAM: Primitive::aam(context.registers.axp(), uint8_t(instruction.operand()), context); return;
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case Operation::AAD: Primitive::aad(context.registers.axp(), uint8_t(instruction.operand()), context); return;
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case Operation::AAA: Primitive::aaas<true>(context.registers.axp(), context); return;
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case Operation::AAS: Primitive::aaas<false>(context.registers.axp(), context); return;
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case Operation::DAA: Primitive::daas<true>(context.registers.al(), context); return;
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case Operation::DAS: Primitive::daas<false>(context.registers.al(), context); return;
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case Operation::CBW: Primitive::cbw(pair_low()); return;
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case Operation::CWD: Primitive::cwd(pair_high(), pair_low()); return;
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case Operation::HLT: context.flow_controller.halt(); return;
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case Operation::WAIT: context.flow_controller.wait(); return;
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case Operation::ADC:
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Primitive::add<true, IntT>(destination_rmw(), source_r(), context);
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break;
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case Operation::ADD:
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Primitive::add<false, IntT>(destination_rmw(), source_r(), context);
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break;
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case Operation::SBB:
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Primitive::sub<true, AccessType::ReadModifyWrite, IntT>(destination_rmw(), source_r(), context);
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break;
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case Operation::SUB:
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Primitive::sub<false, AccessType::ReadModifyWrite, IntT>(destination_rmw(), source_r(), context);
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break;
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case Operation::CMP:
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Primitive::sub<false, AccessType::Read, IntT>(destination_r(), source_r(), context);
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return;
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case Operation::TEST:
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Primitive::test<IntT>(destination_r(), source_r(), context);
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return;
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case Operation::MUL: Primitive::mul<IntT>(pair_high(), pair_low(), source_r(), context); return;
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case Operation::IMUL_1: Primitive::imul<IntT>(pair_high(), pair_low(), source_r(), context); return;
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case Operation::DIV: Primitive::div<IntT>(pair_high(), pair_low(), source_r(), context); return;
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case Operation::IDIV: Primitive::idiv<false, IntT>(pair_high(), pair_low(), source_r(), context); return;
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case Operation::IDIV_REP:
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if constexpr (ContextT::model == Model::i8086) {
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Primitive::idiv<true, IntT>(pair_high(), pair_low(), source_r(), context);
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break;
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} else {
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static_assert(int(Operation::IDIV_REP) == int(Operation::LEAVE));
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if constexpr (std::is_same_v<IntT, uint16_t> || std::is_same_v<IntT, uint32_t>) {
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Primitive::leave<IntT>();
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}
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}
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return;
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case Operation::INC: Primitive::inc<IntT>(destination_rmw(), context); break;
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case Operation::DEC: Primitive::dec<IntT>(destination_rmw(), context); break;
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case Operation::AND: Primitive::and_<IntT>(destination_rmw(), source_r(), context); break;
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case Operation::OR: Primitive::or_<IntT>(destination_rmw(), source_r(), context); break;
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case Operation::XOR: Primitive::xor_<IntT>(destination_rmw(), source_r(), context); break;
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case Operation::NEG: Primitive::neg<IntT>(source_rmw(), context); break; // TODO: should be a destination.
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case Operation::NOT: Primitive::not_<IntT>(source_rmw()); break; // TODO: should be a destination.
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case Operation::CALLrel:
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Primitive::call_relative<AddressT>(instruction.displacement(), context);
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return;
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case Operation::CALLabs: Primitive::call_absolute<IntT, AddressT>(destination_r(), context); return;
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case Operation::CALLfar: Primitive::call_far<AddressT>(instruction, context); return;
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case Operation::JMPrel: jcc(true); return;
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case Operation::JMPabs: Primitive::jump_absolute<IntT>(destination_r(), context); return;
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case Operation::JMPfar: Primitive::jump_far(instruction, context); return;
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case Operation::JCXZ: jcc(!eCX()); return;
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case Operation::LOOP: Primitive::loop<AddressT>(eCX(), instruction.offset(), context); return;
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case Operation::LOOPE: Primitive::loope<AddressT>(eCX(), instruction.offset(), context); return;
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case Operation::LOOPNE: Primitive::loopne<AddressT>(eCX(), instruction.offset(), context); return;
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case Operation::IRET: Primitive::iret(context); return;
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case Operation::RETnear: Primitive::ret_near(instruction, context); return;
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case Operation::RETfar: Primitive::ret_far(instruction, context); return;
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case Operation::INT: interrupt(instruction.operand(), context); return;
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case Operation::INTO: Primitive::into(context); return;
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case Operation::SAHF: Primitive::sahf(context.registers.ah(), context); return;
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case Operation::LAHF: Primitive::lahf(context.registers.ah(), context); return;
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case Operation::LDS:
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if constexpr (data_size == DataSize::Word) {
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Primitive::ld<Source::DS>(instruction, destination_w(), context);
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context.segments.did_update(Source::DS);
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}
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return;
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case Operation::LES:
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if constexpr (data_size == DataSize::Word) {
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Primitive::ld<Source::ES>(instruction, destination_w(), context);
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context.segments.did_update(Source::ES);
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}
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return;
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case Operation::LEA: Primitive::lea<IntT>(instruction, destination_w(), context); return;
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case Operation::MOV:
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Primitive::mov<IntT>(destination_w(), source_r());
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if constexpr (std::is_same_v<IntT, uint16_t>) {
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context.segments.did_update(instruction.destination().source());
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}
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break;
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case Operation::JO: jcc(context.flags.template condition<Condition::Overflow>()); return;
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case Operation::JNO: jcc(!context.flags.template condition<Condition::Overflow>()); return;
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case Operation::JB: jcc(context.flags.template condition<Condition::Below>()); return;
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case Operation::JNB: jcc(!context.flags.template condition<Condition::Below>()); return;
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case Operation::JZ: jcc(context.flags.template condition<Condition::Zero>()); return;
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case Operation::JNZ: jcc(!context.flags.template condition<Condition::Zero>()); return;
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case Operation::JBE: jcc(context.flags.template condition<Condition::BelowOrEqual>()); return;
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case Operation::JNBE: jcc(!context.flags.template condition<Condition::BelowOrEqual>()); return;
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case Operation::JS: jcc(context.flags.template condition<Condition::Sign>()); return;
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case Operation::JNS: jcc(!context.flags.template condition<Condition::Sign>()); return;
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case Operation::JP: jcc(!context.flags.template condition<Condition::ParityOdd>()); return;
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case Operation::JNP: jcc(context.flags.template condition<Condition::ParityOdd>()); return;
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case Operation::JL: jcc(context.flags.template condition<Condition::Less>()); return;
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case Operation::JNL: jcc(!context.flags.template condition<Condition::Less>()); return;
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case Operation::JLE: jcc(context.flags.template condition<Condition::LessOrEqual>()); return;
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case Operation::JNLE: jcc(!context.flags.template condition<Condition::LessOrEqual>()); return;
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case Operation::RCL: Primitive::rcl<IntT>(destination_rmw(), shift_count(), context); break;
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case Operation::RCR: Primitive::rcr<IntT>(destination_rmw(), shift_count(), context); break;
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case Operation::ROL: Primitive::rol<IntT>(destination_rmw(), shift_count(), context); break;
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case Operation::ROR: Primitive::ror<IntT>(destination_rmw(), shift_count(), context); break;
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case Operation::SAL: Primitive::sal<IntT>(destination_rmw(), shift_count(), context); break;
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case Operation::SAR: Primitive::sar<IntT>(destination_rmw(), shift_count(), context); break;
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case Operation::SHR: Primitive::shr<IntT>(destination_rmw(), shift_count(), context); break;
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case Operation::CLC: Primitive::clc(context); return;
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case Operation::CLD: Primitive::cld(context); return;
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case Operation::CLI: Primitive::cli(context); return;
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case Operation::STC: Primitive::stc(context); return;
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case Operation::STD: Primitive::std(context); return;
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case Operation::STI: Primitive::sti(context); return;
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case Operation::CMC: Primitive::cmc(context); return;
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case Operation::XCHG: Primitive::xchg<IntT>(destination_rmw(), source_rmw()); break;
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case Operation::SALC: Primitive::salc(context.registers.al(), context); return;
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case Operation::SETMO:
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if constexpr (ContextT::model == Model::i8086) {
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Primitive::setmo<IntT>(destination_w(), context);
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break;
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} else {
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static_assert(int(Operation::SETMO) == int(Operation::ENTER));
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Primitive::enter<IntT>(instruction, context);
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}
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return;
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case Operation::SETMOC:
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if constexpr (ContextT::model == Model::i8086) {
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// Test CL out here to avoid taking a reference to memory if
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// no write is going to occur.
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if(context.registers.cl()) {
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Primitive::setmo<IntT>(destination_w(), context);
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}
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break;
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} else {
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static_assert(int(Operation::SETMOC) == int(Operation::BOUND));
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Primitive::bound<IntT>(instruction, destination_r(), source_r(), context);
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}
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return;
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case Operation::OUT: Primitive::out<IntT>(port(instruction.destination().source()), pair_low(), context); return;
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case Operation::IN: Primitive::in<IntT>(port(instruction.source().source()), pair_low(), context); return;
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case Operation::XLAT: Primitive::xlat<AddressT>(instruction, context); return;
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case Operation::POP:
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destination_w() = Primitive::pop<IntT, false>(context);
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if constexpr (std::is_same_v<IntT, uint16_t>) {
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context.segments.did_update(instruction.destination().source());
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}
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break;
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case Operation::PUSH:
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Primitive::push<IntT, false>(source_rmw(), context); // PUSH SP modifies SP before pushing it;
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// hence PUSH is sometimes read-modify-write.
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break;
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case Operation::POPF:
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if constexpr (std::is_same_v<IntT, uint16_t> || std::is_same_v<IntT, uint32_t>) {
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Primitive::popf(context);
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}
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return;
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case Operation::PUSHF:
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if constexpr (std::is_same_v<IntT, uint16_t> || std::is_same_v<IntT, uint32_t>) {
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Primitive::pushf(context);
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}
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return;
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case Operation::POPA:
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if constexpr (std::is_same_v<IntT, uint16_t> || std::is_same_v<IntT, uint32_t>) {
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Primitive::popa<IntT>(context);
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}
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return;
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case Operation::PUSHA:
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if constexpr (std::is_same_v<IntT, uint16_t> || std::is_same_v<IntT, uint32_t>) {
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Primitive::pusha<IntT>(context);
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}
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return;
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case Operation::CMPS:
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Primitive::cmps<IntT, AddressT, Repetition::None>(instruction, eCX(), eSI(), eDI(), context);
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return;
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case Operation::CMPS_REPE:
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Primitive::cmps<IntT, AddressT, Repetition::RepE>(instruction, eCX(), eSI(), eDI(), context);
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return;
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case Operation::CMPS_REPNE:
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Primitive::cmps<IntT, AddressT, Repetition::RepNE>(instruction, eCX(), eSI(), eDI(), context);
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return;
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case Operation::SCAS:
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Primitive::scas<IntT, AddressT, Repetition::None>(eCX(), eDI(), pair_low(), context);
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return;
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case Operation::SCAS_REPE:
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Primitive::scas<IntT, AddressT, Repetition::RepE>(eCX(), eDI(), pair_low(), context);
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return;
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case Operation::SCAS_REPNE:
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Primitive::scas<IntT, AddressT, Repetition::RepNE>(eCX(), eDI(), pair_low(), context);
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return;
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case Operation::LODS:
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Primitive::lods<IntT, AddressT, Repetition::None>(instruction, eCX(), eSI(), pair_low(), context);
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return;
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case Operation::LODS_REP:
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Primitive::lods<IntT, AddressT, Repetition::Rep>(instruction, eCX(), eSI(), pair_low(), context);
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return;
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case Operation::MOVS:
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Primitive::movs<IntT, AddressT, Repetition::None>(instruction, eCX(), eSI(), eDI(), context);
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break;
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case Operation::MOVS_REP:
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Primitive::movs<IntT, AddressT, Repetition::Rep>(instruction, eCX(), eSI(), eDI(), context);
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break;
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case Operation::STOS:
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Primitive::stos<IntT, AddressT, Repetition::None>(eCX(), eDI(), pair_low(), context);
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break;
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case Operation::STOS_REP:
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Primitive::stos<IntT, AddressT, Repetition::Rep>(eCX(), eDI(), pair_low(), context);
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break;
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case Operation::OUTS:
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Primitive::outs<IntT, AddressT, Repetition::None>(instruction, eCX(), context.registers.dx(), eSI(), context);
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return;
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case Operation::OUTS_REP:
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Primitive::outs<IntT, AddressT, Repetition::Rep>(instruction, eCX(), context.registers.dx(), eSI(), context);
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return;
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case Operation::INS:
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Primitive::ins<IntT, AddressT, Repetition::None>(eCX(), context.registers.dx(), eDI(), context);
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break;
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case Operation::INS_REP:
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Primitive::ins<IntT, AddressT, Repetition::Rep>(eCX(), context.registers.dx(), eDI(), context);
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break;
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}
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||
|
||
// Write to memory if required to complete this operation.
|
||
//
|
||
// This is not currently handled via RAII because of the amount of context that would need to place onto the stack;
|
||
// instead code has been set up to make sure there is only at most one writeable target on loan for potential
|
||
// write back. I might flip-flop on this, especially if I can verify whether extra stack context is easily
|
||
// optimised out.
|
||
context.memory.template write_back<IntT>();
|
||
}
|
||
|
||
//
|
||
// Public function; just a trampoline into a version of perform templated on data and address size.
|
||
//
|
||
// Which, yes, means there's an outer switch leading to an inner switch, which could be reduced to one big switch.
|
||
// It'd be a substantial effort to find the most neat expression of that, I think, so it is not currently done.
|
||
//
|
||
template <
|
||
typename InstructionT,
|
||
typename ContextT
|
||
> void perform(
|
||
const InstructionT &instruction,
|
||
ContextT &context
|
||
) {
|
||
auto size = [](DataSize operation_size, AddressSize address_size) constexpr -> int {
|
||
return int(operation_size) + (int(address_size) << 2);
|
||
};
|
||
|
||
// Dispatch to a function specialised on data and address size.
|
||
switch(size(instruction.operation_size(), instruction.address_size())) {
|
||
// 16-bit combinations.
|
||
case size(DataSize::Byte, AddressSize::b16):
|
||
perform<DataSize::Byte, AddressSize::b16>(instruction, context);
|
||
return;
|
||
case size(DataSize::Word, AddressSize::b16):
|
||
perform<DataSize::Word, AddressSize::b16>(instruction, context);
|
||
return;
|
||
|
||
// 32-bit combinations.
|
||
//
|
||
// The if constexprs below ensure that `perform` isn't compiled for incompatible data or address size and
|
||
// model combinations. So if a caller nominates a 16-bit model it can supply registers and memory objects
|
||
// that don't implement 32-bit registers or accesses.
|
||
case size(DataSize::Byte, AddressSize::b32):
|
||
if constexpr (is_32bit(ContextT::model)) {
|
||
perform<DataSize::Byte, AddressSize::b32>(instruction, context);
|
||
return;
|
||
}
|
||
break;
|
||
case size(DataSize::Word, AddressSize::b32):
|
||
if constexpr (is_32bit(ContextT::model)) {
|
||
perform<DataSize::Word, AddressSize::b32>(instruction, context);
|
||
return;
|
||
}
|
||
break;
|
||
case size(DataSize::DWord, AddressSize::b16):
|
||
if constexpr (is_32bit(ContextT::model)) {
|
||
perform<DataSize::DWord, AddressSize::b16>(instruction, context);
|
||
return;
|
||
}
|
||
break;
|
||
case size(DataSize::DWord, AddressSize::b32):
|
||
if constexpr (is_32bit(ContextT::model)) {
|
||
perform<DataSize::DWord, AddressSize::b32>(instruction, context);
|
||
return;
|
||
}
|
||
break;
|
||
|
||
default: break;
|
||
}
|
||
|
||
// This is reachable only if the data and address size combination in use isn't available
|
||
// on the processor model nominated.
|
||
assert(false);
|
||
}
|
||
|
||
template <
|
||
typename ContextT
|
||
> void interrupt(
|
||
int index,
|
||
ContextT &context
|
||
) {
|
||
const uint32_t address = static_cast<uint32_t>(index) << 2;
|
||
context.memory.preauthorise_read(address, sizeof(uint16_t) * 2);
|
||
context.memory.preauthorise_stack_write(sizeof(uint16_t) * 3);
|
||
|
||
const uint16_t ip = context.memory.template access<uint16_t, AccessType::PreauthorisedRead>(address);
|
||
const uint16_t cs = context.memory.template access<uint16_t, AccessType::PreauthorisedRead>(address + 2);
|
||
|
||
auto flags = context.flags.get();
|
||
Primitive::push<uint16_t, true>(flags, context);
|
||
context.flags.template set_from<Flag::Interrupt, Flag::Trap>(0);
|
||
|
||
// Push CS and IP.
|
||
Primitive::push<uint16_t, true>(context.registers.cs(), context);
|
||
Primitive::push<uint16_t, true>(context.registers.ip(), context);
|
||
|
||
// Set new destination.
|
||
context.flow_controller.jump(cs, ip);
|
||
}
|
||
|
||
}
|