mirror of https://github.com/TomHarte/CLK.git
416 lines
13 KiB
C++
416 lines
13 KiB
C++
//
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// CRTC6845.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 31/07/2017.
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// Copyright 2017 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "../../ClockReceiver/ClockReceiver.hpp"
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#include <cstdint>
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#include <cstdio>
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namespace Motorola::CRTC {
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struct BusState {
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bool display_enable = false;
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bool hsync = false;
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bool vsync = false;
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bool cursor = false;
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uint16_t refresh_address = 0;
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uint16_t row_address = 0;
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// Not strictly part of the bus state; provided because the partition between 6845 and bus handler
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// doesn't quite hold up in some emulated systems where the two are integrated and share more state.
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int field_count = 0;
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};
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class BusHandler {
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public:
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/*!
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Performs the first phase of a 6845 bus cycle; this is the phase in which it is intended that
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systems using the 6845 respect the bus state and produce pixels, sync or whatever they require.
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*/
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void perform_bus_cycle_phase1(const BusState &) {}
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/*!
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Performs the second phase of a 6845 bus cycle. Some bus state, including sync, is updated
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directly after phase 1 and hence is visible to an observer during phase 2. Handlers may therefore
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implement @c perform_bus_cycle_phase2 to be notified of the availability of that state without
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having to wait until the next cycle has begun.
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*/
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void perform_bus_cycle_phase2(const BusState &) {}
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};
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enum class Personality {
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HD6845S, // Type 0 in CPC parlance. Zero-width HSYNC available, no status, programmable VSYNC length.
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// Considered exactly identical to the UM6845, so this enum covers both.
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UM6845R, // Type 1 in CPC parlance. Status register, fixed-length VSYNC.
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MC6845, // Type 2. No status register, fixed-length VSYNC, no zero-length HSYNC.
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AMS40226, // Type 3. Status is get register, fixed-length VSYNC, no zero-length HSYNC.
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EGA, // Extended EGA-style CRTC; uses 16-bit addressing throughout.
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};
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constexpr bool is_egavga(Personality p) {
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return p >= Personality::EGA;
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}
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// https://www.pcjs.org/blog/2018/03/20/ advises that "the behavior of bits 5 and 6 [of register 10, the cursor start
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// register is really card specific".
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//
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// This enum captures those specifics.
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enum class CursorType {
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/// No cursor signal is generated.
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None,
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/// MDA style: 00 => symmetric blinking; 01 or 10 => no blinking; 11 => short on, long off.
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MDA,
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/// EGA style: ignore the bits completely.
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EGA,
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};
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// TODO UM6845R and R12/R13; see http://www.cpcwiki.eu/index.php/CRTC#CRTC_Differences
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template <class BusHandlerT, Personality personality, CursorType cursor_type> class CRTC6845 {
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public:
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CRTC6845(BusHandlerT &bus_handler) noexcept :
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bus_handler_(bus_handler), status_(0) {}
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void select_register(uint8_t r) {
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selected_register_ = r;
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}
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uint8_t get_status() {
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switch(personality) {
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case Personality::UM6845R: return status_ | (bus_state_.vsync ? 0x20 : 0x00);
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case Personality::AMS40226: return get_register();
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default: return 0xff;
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}
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return 0xff;
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}
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uint8_t get_register() {
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if(selected_register_ == 31) status_ &= ~0x80;
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if(selected_register_ == 16 || selected_register_ == 17) status_ &= ~0x40;
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if(personality == Personality::UM6845R && selected_register_ == 31) return dummy_register_;
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if(selected_register_ < 12 || selected_register_ > 17) return 0xff;
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return registers_[selected_register_];
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}
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void set_register(uint8_t value) {
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static constexpr bool is_ega = is_egavga(personality);
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auto load_low = [value](uint16_t &target) {
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target = (target & 0xff00) | value;
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};
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auto load_high = [value](uint16_t &target) {
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constexpr uint8_t mask = RefreshMask >> 8;
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target = uint16_t((target & 0x00ff) | ((value & mask) << 8));
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};
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switch(selected_register_) {
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case 0: layout_.horizontal.total = value; break;
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case 1: layout_.horizontal.displayed = value; break;
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case 2: layout_.horizontal.start_sync = value; break;
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case 3:
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layout_.horizontal.sync_width = value & 0xf;
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layout_.vertical.sync_lines = value >> 4;
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// TODO: vertical sync lines:
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// "(0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)"
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break;
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case 4: layout_.vertical.total = value & 0x7f; break;
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case 5: layout_.vertical.adjust = value & 0x1f; break;
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case 6: layout_.vertical.displayed = value & 0x7f; break;
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case 7: layout_.vertical.start_sync = value & 0x7f; break;
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case 8:
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switch(value & 3) {
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default: layout_.interlace_mode_ = InterlaceMode::Off; break;
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case 0b01: layout_.interlace_mode_ = InterlaceMode::InterlaceSync; break;
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case 0b11: layout_.interlace_mode_ = InterlaceMode::InterlaceSyncAndVideo; break;
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}
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// Per CPC documentation, skew doesn't work on a "type 1 or 2", i.e. an MC6845 or a UM6845R.
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if(personality != Personality::UM6845R && personality != Personality::MC6845) {
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switch((value >> 4)&3) {
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default: display_skew_mask_ = 1; break;
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case 1: display_skew_mask_ = 2; break;
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case 2: display_skew_mask_ = 4; break;
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}
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}
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break;
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case 9: layout_.vertical.end_row = value & 0x1f; break;
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case 10:
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layout_.vertical.start_cursor = value & 0x1f;
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layout_.cursor_flags = (value >> 5) & 3;
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break;
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case 11:
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layout_.vertical.end_cursor = value & 0x1f;
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break;
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case 12: load_high(layout_.start_address); break;
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case 13: load_low(layout_.start_address); break;
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case 14: load_high(layout_.cursor_address); break;
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case 15: load_low(layout_.cursor_address); break;
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}
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static constexpr uint8_t masks[] = {
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0xff, // Horizontal total.
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0xff, // Horizontal display end.
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0xff, // Start horizontal blank.
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0xff, //
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// EGA: b0–b4: end of horizontal blank;
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// b5–b6: "Number of character clocks to delay start of display after Horizontal Total has been reached."
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is_ega ? 0xff : 0x7f, // Start horizontal retrace.
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0x1f, 0x7f, 0x7f,
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0xff, 0x1f, 0x7f, 0x1f,
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uint8_t(RefreshMask >> 8), uint8_t(RefreshMask),
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uint8_t(RefreshMask >> 8), uint8_t(RefreshMask),
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};
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if(selected_register_ < 16) {
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registers_[selected_register_] = value & masks[selected_register_];
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}
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if(selected_register_ == 31 && personality == Personality::UM6845R) {
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dummy_register_ = value;
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}
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}
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void trigger_light_pen() {
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registers_[17] = bus_state_.refresh_address & 0xff;
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registers_[16] = bus_state_.refresh_address >> 8;
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status_ |= 0x40;
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}
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void run_for(Cycles cycles) {
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auto cyles_remaining = cycles.as_integral();
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while(cyles_remaining--) {
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// Check for end of visible characters.
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if(character_counter_ == layout_.horizontal.displayed) {
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// TODO: consider skew in character_is_visible_. Or maybe defer until perform_bus_cycle?
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character_is_visible_ = false;
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end_of_line_address_ = bus_state_.refresh_address;
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}
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perform_bus_cycle_phase1();
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bus_state_.refresh_address = (bus_state_.refresh_address + 1) & RefreshMask;
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bus_state_.cursor = is_cursor_line_ &&
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bus_state_.refresh_address == layout_.cursor_address;
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// Check for end-of-line.
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if(character_counter_ == layout_.horizontal.total) {
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character_counter_ = 0;
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do_end_of_line();
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character_is_visible_ = true;
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} else {
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// Increment counter.
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character_counter_++;
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}
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// Check for start of horizontal sync.
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if(character_counter_ == layout_.horizontal.start_sync) {
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hsync_counter_ = 0;
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bus_state_.hsync = true;
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}
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// Check for end of horizontal sync; note that a sync time of zero will result in an immediate
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// cancellation of the plan to perform sync if this is an HD6845S or UM6845R; otherwise zero
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// will end up counting as 16 as it won't be checked until after overflow.
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if(bus_state_.hsync) {
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switch(personality) {
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case Personality::HD6845S:
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case Personality::UM6845R:
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bus_state_.hsync = hsync_counter_ != layout_.horizontal.sync_width;
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hsync_counter_ = (hsync_counter_ + 1) & 15;
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break;
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default:
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hsync_counter_ = (hsync_counter_ + 1) & 15;
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bus_state_.hsync = hsync_counter_ != layout_.horizontal.sync_width;
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break;
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}
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}
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perform_bus_cycle_phase2();
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}
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}
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const BusState &get_bus_state() const {
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return bus_state_;
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}
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private:
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static constexpr uint16_t RefreshMask = (personality >= Personality::EGA) ? 0xffff : 0x3fff;
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inline void perform_bus_cycle_phase1() {
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// Skew theory of operation: keep a history of the last three states, and apply whichever is selected.
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character_is_visible_shifter_ = (character_is_visible_shifter_ << 1) | unsigned(character_is_visible_);
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bus_state_.display_enable = (int(character_is_visible_shifter_) & display_skew_mask_) && line_is_visible_;
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bus_handler_.perform_bus_cycle_phase1(bus_state_);
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}
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inline void perform_bus_cycle_phase2() {
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bus_handler_.perform_bus_cycle_phase2(bus_state_);
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}
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inline void do_end_of_line() {
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if constexpr (cursor_type != CursorType::None) {
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// Check for cursor disable.
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// TODO: this is handled differently on the EGA, should I ever implement that.
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is_cursor_line_ &= bus_state_.row_address != layout_.vertical.end_cursor;
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}
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// Check for end of vertical sync.
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if(bus_state_.vsync) {
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vsync_counter_ = (vsync_counter_ + 1) & 15;
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// On the UM6845R and AMS40226, honour the programmed vertical sync time; on the other CRTCs
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// always use a vertical sync count of 16.
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switch(personality) {
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case Personality::HD6845S:
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case Personality::AMS40226:
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bus_state_.vsync = vsync_counter_ != layout_.vertical.sync_lines;
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break;
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default:
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bus_state_.vsync = vsync_counter_ != 0;
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break;
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}
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}
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if(is_in_adjustment_period_) {
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line_counter_++;
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if(line_counter_ == layout_.vertical.adjust) {
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is_in_adjustment_period_ = false;
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do_end_of_frame();
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}
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} else {
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// Advance vertical counter.
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if(bus_state_.row_address == layout_.vertical.end_row) {
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bus_state_.row_address = 0;
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line_address_ = end_of_line_address_;
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// Check for entry into the overflow area.
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if(line_counter_ == layout_.vertical.total) {
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if(layout_.vertical.adjust) {
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line_counter_ = 0;
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is_in_adjustment_period_ = true;
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} else {
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do_end_of_frame();
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}
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} else {
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line_counter_ = (line_counter_ + 1) & 0x7f;
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// Check for start of vertical sync.
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if(line_counter_ == layout_.vertical.start_sync) {
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bus_state_.vsync = true;
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vsync_counter_ = 0;
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}
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// Check for end of visible lines.
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if(line_counter_ == layout_.vertical.displayed) {
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line_is_visible_ = false;
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}
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}
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} else {
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bus_state_.row_address = (bus_state_.row_address + 1) & 0x1f;
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}
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}
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bus_state_.refresh_address = line_address_;
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character_counter_ = 0;
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character_is_visible_ = (layout_.horizontal.displayed != 0);
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if constexpr (cursor_type != CursorType::None) {
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// Check for cursor enable.
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is_cursor_line_ |= bus_state_.row_address == layout_.vertical.start_cursor;
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switch(cursor_type) {
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// MDA-style blinking.
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// https://retrocomputing.stackexchange.com/questions/27803/what-are-the-blinking-rates-of-the-caret-and-of-blinking-text-on-pc-graphics-car
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// gives an 8/8 pattern for regular blinking though mode 11 is then just a guess.
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case CursorType::MDA:
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switch(layout_.cursor_flags) {
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case 0b11: is_cursor_line_ &= (bus_state_.field_count & 8) < 3; break;
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case 0b00: is_cursor_line_ &= bool(bus_state_.field_count & 8); break;
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case 0b01: is_cursor_line_ = false; break;
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case 0b10: is_cursor_line_ = true; break;
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default: break;
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}
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break;
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}
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}
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}
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inline void do_end_of_frame() {
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line_counter_ = 0;
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line_is_visible_ = true;
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line_address_ = layout_.start_address;
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bus_state_.refresh_address = line_address_;
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++bus_state_.field_count;
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}
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BusHandlerT &bus_handler_;
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BusState bus_state_;
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enum class InterlaceMode {
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Off,
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InterlaceSync,
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InterlaceSyncAndVideo,
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};
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enum class BlinkMode {
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// TODO.
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};
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struct {
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struct {
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uint8_t total;
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uint8_t displayed;
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uint8_t start_sync;
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uint8_t sync_width;
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} horizontal;
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struct {
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uint8_t total;
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uint8_t displayed;
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uint8_t start_sync;
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uint8_t sync_lines;
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uint8_t adjust;
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uint8_t end_row;
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uint8_t start_cursor;
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uint8_t end_cursor;
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} vertical;
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InterlaceMode interlace_mode_ = InterlaceMode::Off;
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uint16_t start_address;
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uint16_t cursor_address;
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uint16_t light_pen_address;
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uint8_t cursor_flags;
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} layout_;
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uint8_t registers_[18]{};
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uint8_t dummy_register_ = 0;
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int selected_register_ = 0;
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uint8_t character_counter_ = 0;
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uint8_t line_counter_ = 0;
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bool character_is_visible_ = false, line_is_visible_ = false;
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int hsync_counter_ = 0;
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int vsync_counter_ = 0;
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bool is_in_adjustment_period_ = false;
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uint16_t line_address_ = 0;
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uint16_t end_of_line_address_ = 0;
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uint8_t status_ = 0;
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int display_skew_mask_ = 1;
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unsigned int character_is_visible_shifter_ = 0;
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bool is_cursor_line_ = false;
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};
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}
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