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CLK/Machines/ZX8081
2017-06-21 21:44:42 -04:00
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Video.cpp Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate. 2017-06-12 18:55:04 -04:00
Video.hpp
ZX8081.cpp Removed some minor duplicity and ensured that hsync/NMI ends on the nominated cycle, not one afterwards. 2017-06-21 21:44:42 -04:00
ZX8081.hpp Restored proper video output. 2017-06-21 21:18:09 -04:00