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234 lines
8.4 KiB
C++
234 lines
8.4 KiB
C++
//
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// 68000Storage.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "../../../InstructionSets/M68k/Decoder.hpp"
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#include "../../../InstructionSets/M68k/Perform.hpp"
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#include "../../../InstructionSets/M68k/Status.hpp"
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#include <limits>
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namespace CPU::MC68000 {
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struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
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ProcessorBase() {
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read_program_announce.address = read_program.address = &program_counter_.l;
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}
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ProcessorBase(const ProcessorBase& rhs) = delete;
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ProcessorBase& operator=(const ProcessorBase& rhs) = delete;
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int state_ = 0;
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/// Counts time left on the clock before the current batch of processing
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/// is complete; may be less than zero.
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HalfCycles time_remaining_;
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/// E clock phase.
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HalfCycles e_clock_phase_;
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/// Current supervisor state, for direct provision to the bus handler.
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int is_supervisor_ = 1;
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// A decoder for instructions, plus all collected information about the
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// current instruction.
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InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> decoder_;
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InstructionSet::M68k::Preinstruction instruction_;
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uint16_t opcode_;
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uint8_t operand_flags_;
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SlicedInt32 instruction_address_;
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// Register state.
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InstructionSet::M68k::Status status_;
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SlicedInt32 program_counter_;
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SlicedInt32 registers_[16]{}; // D0–D7 followed by A0–A7.
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SlicedInt32 stack_pointers_[2];
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/// Current state of the DTACK input.
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bool dtack_ = false;
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/// Current state of the VPA input.
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bool vpa_ = false;
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/// Current state of the BERR input.
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bool berr_ = false;
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/// Current input interrupt level.
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int bus_interrupt_level_ = 0;
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// Whether to trace at the end of this instruction.
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InstructionSet::M68k::Status::FlagT should_trace_ = 0;
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// I don't have great information on the 68000 interrupt latency; as a first
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// guess, capture the bus interrupt level upon every prefetch, and use that for
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// the inner-loop decision.
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int captured_interrupt_level_ = 0;
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/// Contains the prefetch queue; the most-recently fetched thing is the
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/// low portion of this word, and the thing fetched before that has
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/// proceeded to the high portion.
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SlicedInt32 prefetch_;
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// Temporary storage for the current instruction's operands
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// and the corresponding effective addresses.
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CPU::SlicedInt32 operand_[2];
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CPU::SlicedInt32 effective_address_[2];
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/// If currently in the wait-for-DTACK state, this indicates where to go
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/// upon receipt of DTACK or VPA. BERR will automatically segue
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/// into the proper exception.
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int post_dtack_state_ = 0;
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/// If using CalcEffectiveAddress, this is the state to adopt after the
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/// effective address for next_operand_ has been calculated.
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int post_ea_state_ = 0;
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/// The perform state for this operation.
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int perform_state_ = 0;
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/// When fetching or storing operands, this is the next one to fetch
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/// or store.
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int next_operand_ = -1;
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/// Storage for a temporary address, which can't be a local because it'll
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/// be used to populate microcycles, which may persist beyond an entry
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/// and exit of run_for (especially between an address announcement, and
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/// a data select).
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SlicedInt32 temporary_address_;
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/// Storage for a temporary value; primarily used by MOVEP to split a 32-bit
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/// source into bus-compatible byte units.
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SlicedInt32 temporary_value_;
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/// A record of the exception to trigger.
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int exception_vector_ = 0;
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/// Transient storage for exception processing.
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SlicedInt16 captured_status_;
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/// An internal flag used during various dynamically-sized instructions
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/// (e.g. BCHG, DIVU) to indicate how much additional processing happened;
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/// this is measured in microcycles.
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int dynamic_instruction_length_ = 0;
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/// Two bits of state for MOVEM, being the curent register and what to
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/// add to it to get to the next register.
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int register_index_ = 0, register_delta_ = 0;
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// A lookup table that aids with effective address calculation in
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// predecrement and postincrement modes; index as [size][register]
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// and note that [0][7] is 2 rather than 1.
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static constexpr uint32_t address_increments[3][8] = {
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{ 1, 1, 1, 1, 1, 1, 1, 2, },
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{ 2, 2, 2, 2, 2, 2, 2, 2, },
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{ 4, 4, 4, 4, 4, 4, 4, 4, },
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};
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// A lookup table that ensures write-back to data registers affects
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// only the correct bits.
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static constexpr uint32_t size_masks[3] = { 0xff, 0xffff, 0xffff'ffff };
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// Assumptions used by the lookup tables above:
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static_assert(int(InstructionSet::M68k::DataSize::Byte) == 0);
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static_assert(int(InstructionSet::M68k::DataSize::Word) == 1);
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static_assert(int(InstructionSet::M68k::DataSize::LongWord) == 2);
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/// Used by some dedicated read-modify-write perform patterns to
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/// determine the size of the bus operation.
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OperationT select_flag_ = 0;
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// Captured bus/address-error state.
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Microcycle<Operation::DecodeDynamically> bus_error_;
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// Flow controller methods implemented.
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using Preinstruction = InstructionSet::M68k::Preinstruction;
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template <typename IntT> void did_mulu(IntT);
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template <typename IntT> void did_muls(IntT);
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inline void did_chk(bool, bool);
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inline void did_scc(bool);
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template <typename IntT> void did_shift(int);
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template <bool did_overflow> void did_divu(uint32_t, uint32_t);
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template <bool did_overflow> void did_divs(int32_t, int32_t);
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inline void did_bit_op(int);
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inline void did_update_status();
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template <typename IntT> void complete_bcc(bool, IntT);
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inline void complete_dbcc(bool, bool, int16_t);
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inline void move_to_usp(uint32_t);
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inline void move_from_usp(uint32_t &);
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inline void tas(Preinstruction, uint32_t);
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template <bool use_current_instruction_pc = true> void raise_exception(int);
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// These aren't implemented because the specific details of the implementation
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// mean that the performer call-out isn't necessary.
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template <typename IntT> void movep(Preinstruction, uint32_t, uint32_t) {}
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template <typename IntT> void movem_toM(Preinstruction, uint32_t, uint32_t) {}
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template <typename IntT> void movem_toR(Preinstruction, uint32_t, uint32_t) {}
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void jsr(uint32_t) {}
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void bsr(uint32_t) {}
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void jmp(uint32_t) {}
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inline void pea(uint32_t) {}
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inline void link(Preinstruction, uint32_t) {}
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inline void unlink(uint32_t &) {}
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inline void rtr() {}
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inline void rte() {}
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inline void rts() {}
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inline void reset() {}
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inline void stop() {}
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// Some microcycles that will be modified as required and used in the main loop;
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// the semantics of a switch statement make in-place declarations awkward and
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// some of these may persist across multiple calls to run_for.
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Microcycle<OperationT(0)> idle;
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// Read a program word. All accesses via the program counter are word sized.
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static constexpr OperationT
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ReadProgramAnnounceOperation = Operation::Read | Operation::NewAddress | Operation::IsProgram;
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static constexpr OperationT
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ReadProgramOperation = Operation::Read | Operation::SameAddress | Operation::SelectWord | Operation::IsProgram;
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Microcycle<ReadProgramAnnounceOperation> read_program_announce{};
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Microcycle<ReadProgramOperation> read_program{};
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// Read a data word or byte.
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Microcycle<Operation::DecodeDynamically> access_announce {
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Operation::Read | Operation::NewAddress | Operation::IsData
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};
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Microcycle<Operation::DecodeDynamically> access {
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Operation::Read | Operation::SameAddress | Operation::SelectWord | Operation::IsData
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};
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// TAS.
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static constexpr OperationT
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TASOperations[5] = {
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Operation::Read | Operation::NewAddress | Operation::IsData,
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Operation::Read | Operation::SameAddress | Operation::IsData | Operation::SelectByte,
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Operation::SameAddress,
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Operation::SameAddress | Operation::IsData,
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Operation::SameAddress | Operation::IsData | Operation::SelectByte,
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};
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Microcycle<TASOperations[0]> tas_cycle0;
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Microcycle<TASOperations[1]> tas_cycle1;
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Microcycle<TASOperations[2]> tas_cycle2;
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Microcycle<TASOperations[3]> tas_cycle3;
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Microcycle<TASOperations[4]> tas_cycle4;
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// Reset.
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static constexpr OperationT ResetOperation = CPU::MC68000::Operation::Reset;
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Microcycle<ResetOperation> reset_cycle { HalfCycles(248) };
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// Interrupt acknowledge.
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static constexpr OperationT
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InterruptCycleOperations[2] = {
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Operation::InterruptAcknowledge | Operation::Read | Operation::NewAddress,
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Operation::InterruptAcknowledge | Operation::Read | Operation::SameAddress | Operation::SelectByte
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};
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Microcycle<InterruptCycleOperations[0]> interrupt_cycle0;
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Microcycle<InterruptCycleOperations[1]> interrupt_cycle1;
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// Holding spot when awaiting DTACK/etc.
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Microcycle<Operation::DecodeDynamically> awaiting_dtack;
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};
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}
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