mirror of https://github.com/TomHarte/CLK.git
293 lines
6.8 KiB
C++
293 lines
6.8 KiB
C++
//
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// RealTimeClock.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 07/05/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include <array>
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namespace Apple::Clock {
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/*!
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Models Apple's real-time clocks, as contained in the Macintosh and IIgs.
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Since tracking of time is pushed to this class, it is assumed
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that whomever is translating real time into emulated time
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will also signal interrupts — this is just the storage and time counting.
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*/
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class ClockStorage {
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public:
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/*!
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Advances the clock by 1 second.
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The caller should also signal an interrupt if applicable.
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*/
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void update() {
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for(size_t c = 0; c < 4; ++c) {
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++seconds_[c];
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if(seconds_[c]) break;
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}
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}
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/*!
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Sets the current [P/B]RAM contents.
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*/
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template <typename CollectionT> void set_data(const CollectionT &collection) {
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set_data(collection.begin(), collection.end());
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}
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template <typename IteratorT> void set_data(IteratorT begin, const IteratorT end) {
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size_t c = 0;
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while(begin != end && c < 256) {
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data_[c] = *begin;
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++begin;
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++c;
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}
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}
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protected:
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static constexpr uint16_t NoResult = 0x100;
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static constexpr uint16_t DidComplete = 0x101;
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uint16_t perform(uint8_t command) {
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/*
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Documented commands:
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z0000001 Seconds register 0 (lowest order byte)
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z0000101 Seconds register 1
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z0001001 Seconds register 2
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z0001101 Seconds register 3
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00110001 Test register (write only)
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00110101 Write-protect register (write only)
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z010aa01 RAM addresses 0x10 - 0x13
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z1aaaa01 RAM addresses 0x00 – 0x0f
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z0111abc, followed by 0defgh00
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RAM address abcdefgh
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z = 1 => a read; z = 0 => a write.
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The top bit of the write-protect register enables (0) or disables (1)
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writes to other locations.
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All the documentation says about the test register is to set the top
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two bits to 0 for normal operation. Abnormal operation is undefined.
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*/
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switch(phase_) {
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case Phase::Command:
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// Decode an address.
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switch(command & 0x70) {
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default:
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if(command & 0x40) {
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// RAM addresses 0x00 – 0x0f.
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address_ = (command >> 2) & 0xf;
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} else return DidComplete; // Unrecognised.
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break;
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case 0x00:
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// A time access.
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address_ = SecondsBuffer + ((command >> 2)&3);
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break;
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case 0x30:
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// Either a register access or an extended instruction.
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if(command & 0x08) {
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address_ = unsigned((command & 0x7) << 5);
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phase_ = (command & 0x80) ? Phase::SecondAddressByteRead : Phase::SecondAddressByteWrite;
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return NoResult;
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} else {
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address_ = (command & 4) ? RegisterWriteProtect : RegisterTest;
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}
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break;
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case 0x20:
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// RAM addresses 0x10 – 0x13.
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address_ = 0x10 + ((command >> 2) & 0x3);
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break;
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}
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// If this is a read, return a result; otherwise prepare to write.
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if(command & 0x80) {
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// The two registers are write-only.
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if(address_ == RegisterTest || address_ == RegisterWriteProtect) {
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return DidComplete;
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}
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return (address_ >= SecondsBuffer) ? seconds_[address_ & 0xff] : data_[address_];
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}
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phase_ = Phase::WriteData;
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return NoResult;
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case Phase::SecondAddressByteRead:
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case Phase::SecondAddressByteWrite:
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if(command & 0x83) {
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return DidComplete;
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}
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address_ |= command >> 2;
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if(phase_ == Phase::SecondAddressByteRead) {
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phase_ = Phase::Command;
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return data_[address_]; // Only RAM accesses can get this far.
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} else {
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phase_ = Phase::WriteData;
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}
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return NoResult;
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case Phase::WriteData:
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// First test: is this to the write-protect register?
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if(address_ == RegisterWriteProtect) {
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write_protect_ = command;
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return DidComplete;
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}
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if(address_ == RegisterTest) {
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// No documentation here.
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return DidComplete;
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}
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// No other writing is permitted if the write protect
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// register won't allow it.
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if(!(write_protect_ & 0x80)) {
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if(address_ >= SecondsBuffer) {
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seconds_[address_ & 0xff] = command;
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} else {
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data_[address_] = command;
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}
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}
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phase_ = Phase::Command;
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return DidComplete;
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}
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return NoResult;
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}
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private:
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std::array<uint8_t, 256> data_{0xff};
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std::array<uint8_t, 4> seconds_{};
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uint8_t write_protect_ = 0;
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unsigned int address_ = 0;
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static constexpr int SecondsBuffer = 0x100;
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static constexpr int RegisterTest = 0x200;
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static constexpr int RegisterWriteProtect = 0x201;
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enum class Phase {
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Command,
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SecondAddressByteRead,
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SecondAddressByteWrite,
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WriteData
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};
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Phase phase_ = Phase::Command;
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};
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/*!
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Provides the serial interface implemented by the Macintosh.
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*/
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class SerialClock: public ClockStorage {
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public:
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/*!
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Sets the current clock and data inputs to the clock.
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*/
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void set_input(bool clock, bool data) {
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// The data line is valid when the clock transitions to level 0.
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if(clock && !previous_clock_) {
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// Shift into the command_ register, no matter what.
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command_ = uint16_t((command_ << 1) | (data ? 1 : 0));
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result_ <<= 1;
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// Increment phase.
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++phase_;
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// If a whole byte has been collected, push it onwards.
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if(!(phase_&7)) {
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// Begin pessimistically.
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const auto effect = perform(uint8_t(command_));
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switch(effect) {
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case ClockStorage::NoResult:
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break;
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default:
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result_ = uint8_t(effect);
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break;
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case ClockStorage::DidComplete:
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abort();
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break;
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}
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}
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}
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previous_clock_ = clock;
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}
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/*!
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Reads the current data output level from the clock.
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*/
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bool get_data() {
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return !!(result_ & 0x80);
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}
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/*!
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Announces that a serial command has been aborted.
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*/
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void abort() {
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result_ = 0;
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phase_ = 0;
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command_ = 0;
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}
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private:
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int phase_ = 0;
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uint16_t command_;
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uint8_t result_ = 0;
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bool previous_clock_ = false;
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};
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/*!
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Provides the parallel interface implemented by the IIgs.
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*/
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class ParallelClock: public ClockStorage {
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public:
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void set_control(uint8_t control) {
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if(!(control&0x80)) return;
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if(control & 0x40) {
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// Read from the RTC.
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// A no-op for now.
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} else {
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// Write to the RTC. Which in this implementation also sets up a future read.
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const auto result = perform(data_);
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if(result < 0x100) {
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data_ = uint8_t(result);
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}
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}
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// MAGIC! The transaction took 0 seconds.
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// TODO: no magic.
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control_ = control & 0x7f;
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// Bit 5 is also meant to be 1 or 0 to indicate the final byte.
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}
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uint8_t get_control() {
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return control_;
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}
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void set_data(uint8_t data) {
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data_ = data;
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}
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uint8_t get_data() {
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return data_;
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}
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private:
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uint8_t data_;
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uint8_t control_;
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};
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}
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