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487 lines
14 KiB
C++
487 lines
14 KiB
C++
//
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// Decoder.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/04/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#include "Decoder.hpp"
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#include <cassert>
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using namespace InstructionSet::M68k;
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namespace {
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/// @returns The @c AddressingMode given the specified mode and reg, subject to potential
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/// aliasing on the '020+ as described above the @c AddressingMode enum.
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constexpr AddressingMode combined_mode(int mode, int reg) {
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return (mode != 7) ? AddressingMode(mode) : AddressingMode(0b01'000 | reg);
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}
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}
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// MARK: - Instruction decoders.
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template <Operation operation> Preinstruction Predecoder::decode(uint16_t instruction) {
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// Fields used pervasively below.
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//
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// Underlying assumption: the compiler will discard whatever of these
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// isn't actually used.
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const auto ea_register = instruction & 7;
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const auto ea_mode = (instruction >> 3) & 7;
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const auto ea_combined_mode = combined_mode(ea_mode, ea_register);
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const auto opmode = (instruction >> 6) & 7;
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const auto data_register = (instruction >> 9) & 7;
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switch(operation) {
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//
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// MARK: ABCD, SBCD.
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//
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case Operation::ABCD: case Operation::SBCD: {
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const auto addressing_mode = (instruction & 8) ?
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AddressingMode::AddressRegisterIndirectWithPredecrement : AddressingMode::DataRegisterDirect;
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return Preinstruction(operation,
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addressing_mode, ea_register,
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addressing_mode, data_register);
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}
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//
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// MARK: AND, OR, EOR.
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//
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case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
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case Operation::ORb: case Operation::ORw: case Operation::ORl:
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case Operation::EORb: case Operation::EORw: case Operation::EORl: {
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// Opmode 7 is illegal.
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if(opmode == 7) {
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return Preinstruction();
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}
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constexpr bool is_eor = operation == Operation::EORb || operation == Operation::EORw || operation == Operation::EORl;
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if(opmode & 4) {
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// Dn Λ < ea > → < ea >
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// The operations other than EOR do not permit <ea>
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// to be a data register; targetting a data register
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// should be achieved with the alternative opmode.
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if constexpr (!is_eor) {
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if(ea_combined_mode == AddressingMode::DataRegisterDirect) {
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return Preinstruction();
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}
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}
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return Preinstruction(operation,
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AddressingMode::DataRegisterDirect, data_register,
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ea_combined_mode, ea_register);
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} else {
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// < ea > Λ Dn → Dn
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// EOR doesn't permit → Dn.
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if constexpr (is_eor) {
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return Preinstruction();
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}
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return Preinstruction(operation,
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ea_combined_mode, ea_register,
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AddressingMode::DataRegisterDirect, data_register);
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}
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return Preinstruction();
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}
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//
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// MARK: EXG.
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//
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case Operation::EXG:
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switch((instruction >> 3)&31) {
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default: return Preinstruction();
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case 0x08: return Preinstruction(operation,
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AddressingMode::DataRegisterDirect, ea_register,
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AddressingMode::DataRegisterDirect, data_register);
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case 0x09: return Preinstruction(operation,
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AddressingMode::AddressRegisterDirect, ea_register,
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AddressingMode::AddressRegisterDirect, data_register);
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case 0x11: return Preinstruction(operation,
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AddressingMode::AddressRegisterDirect, ea_register,
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AddressingMode::DataRegisterDirect, data_register);
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}
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//
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// MARK: MULU, MULS, DIVU, DIVS.
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//
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case Operation::DIVU: case Operation::DIVS:
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case Operation::MULU: case Operation::MULS:
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return Preinstruction(operation,
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ea_combined_mode, ea_register,
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AddressingMode::DataRegisterDirect, data_register);
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default:
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// Should be unreachable.
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assert(false);
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}
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// TODO: be careful that decoders for ADD, SUB, etc, must check the instruction a little
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// further to determine whether they're ADDI, SUBI, etc or the regular versions.
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// TODO: be willing to mutate Scc into DBcc.
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}
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// MARK: - Page decoders.
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Preinstruction Predecoder::decode0(uint16_t instruction) {
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switch(instruction) {
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case 0x003c: return decode<Operation::ORItoCCR>(instruction);
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case 0x007c: return decode<Operation::ORItoSR>(instruction);
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case 0x023c: return decode<Operation::ANDItoCCR>(instruction);
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case 0x027c: return decode<Operation::ANDItoSR>(instruction);
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case 0x0a3c: return decode<Operation::EORItoCCR>(instruction);
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case 0x0a7c: return decode<Operation::EORItoSR>(instruction);
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default: break;
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}
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switch(instruction & 0xfc0) {
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// 4-153 (p257)
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case 0x000: return decode<Operation::ORb>(instruction);
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case 0x040: return decode<Operation::ORw>(instruction);
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case 0x080: return decode<Operation::ORl>(instruction);
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// 4-18 (p122)
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case 0x200: return decode<Operation::ANDb>(instruction);
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case 0x240: return decode<Operation::ANDw>(instruction);
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case 0x280: return decode<Operation::ANDl>(instruction);
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// 4-179 (p283)
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case 0x400: return decode<Operation::SUBb>(instruction);
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case 0x440: return decode<Operation::SUBw>(instruction);
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case 0x480: return decode<Operation::SUBl>(instruction);
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// 4-9 (p113)
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case 0x600: return decode<Operation::ADDb>(instruction);
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case 0x640: return decode<Operation::ADDw>(instruction);
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case 0x680: return decode<Operation::ADDl>(instruction);
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// 4-63 (p167)
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case 0x800: return decode<Operation::BTSTb>(instruction);
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// 4-29 (p133)
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case 0x840: return decode<Operation::BCHGb>(instruction);
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// 4-32 (p136)
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case 0x880: return decode<Operation::BCLRb>(instruction);
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// 4-58 (p162)
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case 0x8c0: return decode<Operation::BSETb>(instruction);
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// 4-102 (p206)
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case 0xa00: return decode<Operation::EORb>(instruction);
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case 0xa40: return decode<Operation::EORw>(instruction);
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case 0xa80: return decode<Operation::EORl>(instruction);
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// 4-79 (p183)
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case 0xc00: return decode<Operation::CMPb>(instruction);
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case 0xc40: return decode<Operation::CMPw>(instruction);
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case 0xc80: return decode<Operation::CMPl>(instruction);
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default: break;
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}
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switch(instruction & 0x1c0) {
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case 0x100: return decode<Operation::BTSTb>(instruction); // 4-62 (p166)
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case 0x180: return decode<Operation::BCLRb>(instruction); // 4-31 (p135)
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case 0x140: return decode<Operation::BCHGb>(instruction); // 4-28 (p132)
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case 0x1c0: return decode<Operation::BSETb>(instruction); // 4-57 (p161)
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default: break;
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}
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switch(instruction & 0x1f8) {
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// 4-133 (p237)
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case 0x108: return decode<Operation::MOVEPtoRw>(instruction);
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case 0x148: return decode<Operation::MOVEPtoRl>(instruction);
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case 0x188: return decode<Operation::MOVEPtoMw>(instruction);
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case 0x1c8: return decode<Operation::MOVEPtoMl>(instruction);
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default: break;
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}
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return Preinstruction();
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}
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Preinstruction Predecoder::decode1(uint16_t instruction) {
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return decode<Operation::MOVEb>(instruction);
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}
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Preinstruction Predecoder::decode2(uint16_t instruction) {
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return decode<Operation::MOVEl>(instruction);
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}
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Preinstruction Predecoder::decode3(uint16_t instruction) {
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return decode<Operation::MOVEw>(instruction);
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}
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Preinstruction Predecoder::decode4(uint16_t instruction) {
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switch(instruction & 0xfff) {
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case 0xe70: return decode<Operation::RESET>(instruction); // 6-83 (p537)
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case 0xe71: return decode<Operation::NOP>(instruction); // 8-13 (p469)
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case 0xe73: return decode<Operation::RTE>(instruction); // 6-84 (p538)
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case 0xe75: return decode<Operation::RTS>(instruction); // 4-169 (p273)
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case 0xe76: return decode<Operation::TRAPV>(instruction); // 4-191 (p295)
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case 0xe77: return decode<Operation::RTR>(instruction); // 4-168 (p272)
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default: break;
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}
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switch(instruction & 0xfc0) {
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// 4-146 (p250)
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case 0x000: return decode<Operation::NEGXb>(instruction);
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case 0x040: return decode<Operation::NEGXw>(instruction);
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case 0x080: return decode<Operation::NEGXl>(instruction);
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// 6-17 (p471)
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case 0x0c0: return decode<Operation::MOVEfromSR>(instruction);
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// 4-73 (p177)
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case 0x200: return decode<Operation::CLRb>(instruction);
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case 0x240: return decode<Operation::CLRw>(instruction);
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case 0x280: return decode<Operation::CLRl>(instruction);
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// 4-144 (p248)
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case 0x400: return decode<Operation::NEGb>(instruction);
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case 0x440: return decode<Operation::NEGw>(instruction);
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case 0x480: return decode<Operation::NEGl>(instruction);
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// 4-123 (p227)
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case 0x4c0: return decode<Operation::MOVEtoCCR>(instruction);
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// 4-148 (p250)
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case 0x600: return decode<Operation::NOTb>(instruction);
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case 0x640: return decode<Operation::NOTw>(instruction);
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case 0x680: return decode<Operation::NOTl>(instruction);
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// 4-123 (p227)
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case 0x6c0: return decode<Operation::MOVEtoSR>(instruction);
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// 4-142 (p246)
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case 0x800: return decode<Operation::NBCD>(instruction);
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// 4-159 (p263)
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case 0x840: return decode<Operation::PEA>(instruction);
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// 4-128 (p232)
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case 0x880: return decode<Operation::MOVEMtoMw>(instruction);
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case 0x8c0: return decode<Operation::MOVEMtoMl>(instruction);
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case 0xc80: return decode<Operation::MOVEMtoRw>(instruction);
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case 0xcc0: return decode<Operation::MOVEMtoRl>(instruction);
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// 4-192 (p296)
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case 0xa00: return decode<Operation::TSTb>(instruction);
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case 0xa40: return decode<Operation::TSTw>(instruction);
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case 0xa80: return decode<Operation::TSTl>(instruction);
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// 4-186 (p290)
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case 0xac0: return decode<Operation::TAS>(instruction);
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// 4-109 (p213)
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case 0xe80: return decode<Operation::JSR>(instruction);
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// 4-108 (p212)
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case 0xec0: return decode<Operation::JMP>(instruction);
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default: break;
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}
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switch(instruction & 0x1c0) {
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case 0x1c0: return decode<Operation::MOVEAl>(instruction); // 4-110 (p214)
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case 0x180: return decode<Operation::CHK>(instruction); // 4-69 (p173)
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default: break;
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}
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switch(instruction & 0xff0) {
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case 0xe40: return decode<Operation::TRAP>(instruction); // 4-188 (p292)
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// case 0xe60: return decode<Operation::MOVEtoUSP>(instruction); // 6-21 (p475)
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default: break;
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}
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// TODO: determine MOVEtoUSP and MOVEfromUSP.
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switch(instruction & 0xff8) {
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case 0xe60: return decode<Operation::SWAP>(instruction); // 4-185 (p289)
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case 0x880: return decode<Operation::EXTbtow>(instruction); // 4-106 (p210)
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case 0x8c0: return decode<Operation::EXTwtol>(instruction); // 4-106 (p210)
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case 0xe50: return decode<Operation::LINK>(instruction); // 4-111 (p215)
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case 0xe58: return decode<Operation::UNLINK>(instruction); // 4-194 (p298)
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default: break;
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}
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return Preinstruction();
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}
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Preinstruction Predecoder::decode5(uint16_t instruction) {
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switch(instruction & 0x1c0) {
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// 4-11 (p115)
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case 0x000: return decode<Operation::ADDQb>(instruction);
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case 0x040: return decode<Operation::ADDQw>(instruction);
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case 0x080: return decode<Operation::ADDQl>(instruction);
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// 4-181 (p285)
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case 0x100: return decode<Operation::SUBQb>(instruction);
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case 0x140: return decode<Operation::SUBQw>(instruction);
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case 0x180: return decode<Operation::SUBQl>(instruction);
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default: break;
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}
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switch(instruction & 0x0c0) {
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// 4-173 (p276), though this'll also hit DBcc 4-91 (p195)
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case 0x0c0: return decode<Operation::Scc>(instruction);
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default: break;
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}
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return Preinstruction();
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}
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Preinstruction Predecoder::decode6(uint16_t instruction) {
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// 4-25 (p129), 4-59 (p163) and 4-55 (p159)
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return decode<Operation::Bcc>(instruction);
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}
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Preinstruction Predecoder::decode7(uint16_t instruction) {
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// 4-134 (p238)
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return decode<Operation::MOVEq>(instruction);
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}
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Preinstruction Predecoder::decode8(uint16_t instruction) {
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// 4-171 (p275)
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if((instruction & 0x1f0) == 0x100) return decode<Operation::SBCD>(instruction);
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// 4-150 (p254)
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switch(instruction & 0x0c0) {
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case 0x00: return decode<Operation::ORb>(instruction);
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case 0x40: return decode<Operation::ORw>(instruction);
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case 0x80: return decode<Operation::ORl>(instruction);
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default: break;
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}
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switch(instruction & 0x1c0) {
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case 0x0c0: return decode<Operation::DIVU>(instruction); // 4-97 (p201)
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case 0x1c0: return decode<Operation::DIVS>(instruction); // 4-93 (p197)
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default: break;
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}
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return Preinstruction();
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}
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Preinstruction Predecoder::decode9(uint16_t instruction) {
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(void)instruction;
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return Preinstruction();
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}
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Preinstruction Predecoder::decodeA(uint16_t) {
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return Preinstruction();
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}
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Preinstruction Predecoder::decodeB(uint16_t instruction) {
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// 4-100 (p204)
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switch(instruction & 0x0c0) {
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case 0x000: return decode<Operation::EORb>(instruction);
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case 0x040: return decode<Operation::EORw>(instruction);
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case 0x080: return decode<Operation::EORl>(instruction);
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default: break;
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}
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// 4-75 (p179)
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switch(instruction & 0x1c0) {
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case 0x000: return decode<Operation::CMPb>(instruction);
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case 0x040: return decode<Operation::CMPw>(instruction);
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case 0x080: return decode<Operation::CMPl>(instruction);
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// 4-77 (p181)
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case 0x0c0: return decode<Operation::CMPAw>(instruction);
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case 0x1c0: return decode<Operation::CMPAl>(instruction);
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default: break;
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}
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return Preinstruction();
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}
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Preinstruction Predecoder::decodeC(uint16_t instruction) {
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// 4-3 (p107)
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if((instruction & 0x1f0) == 0x100) return decode<Operation::ABCD>(instruction);
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// 4-15 (p119)
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switch(instruction & 0x0c0) {
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case 0x00: return decode<Operation::ANDb>(instruction);
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case 0x40: return decode<Operation::ANDw>(instruction);
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case 0x80: return decode<Operation::ANDl>(instruction);
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default: break;
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}
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switch(instruction & 0x1c0) {
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case 0x0c0: return decode<Operation::MULU>(instruction); // 4-139 (p243)
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case 0x1c0: return decode<Operation::MULS>(instruction); // 4-136 (p240)
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default: break;
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}
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// 4-105 (p209)
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switch(instruction & 0x1f8) {
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case 0x140:
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case 0x148:
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case 0x188: return decode<Operation::EXG>(instruction);
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}
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return Preinstruction();
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}
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Preinstruction Predecoder::decodeD(uint16_t instruction) {
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(void)instruction;
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return Preinstruction();
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}
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Preinstruction Predecoder::decodeE(uint16_t instruction) {
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(void)instruction;
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return Preinstruction();
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}
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Preinstruction Predecoder::decodeF(uint16_t) {
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return Preinstruction();
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}
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// MARK: - Main decoder.
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Preinstruction Predecoder::decode(uint16_t instruction) {
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// Divide first based on line.
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switch(instruction & 0xf000) {
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case 0x0000: return decode0(instruction);
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case 0x1000: return decode1(instruction);
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case 0x2000: return decode2(instruction);
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case 0x3000: return decode3(instruction);
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case 0x4000: return decode4(instruction);
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case 0x5000: return decode5(instruction);
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case 0x6000: return decode6(instruction);
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case 0x7000: return decode7(instruction);
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case 0x8000: return decode8(instruction);
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case 0x9000: return decode9(instruction);
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case 0xa000: return decodeA(instruction);
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case 0xb000: return decodeB(instruction);
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case 0xc000: return decodeC(instruction);
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case 0xd000: return decodeD(instruction);
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case 0xe000: return decodeE(instruction);
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case 0xf000: return decodeF(instruction);
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default: break;
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}
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return Preinstruction();
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}
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