Thomas Harte 9a91ae38c1 Differentiates reasons for a read to be four cycles. ...

Specifically, puts the enforced wait either before or after checking the wait line. More research may be required; it feels more likely to me that a forced post wait should complete the read then wait, but would that still count as a single machine cycle?

2018-06-20 21:34:21 -04:00

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AllRAM

Removes all instances of the copyright symbol.

2018-05-13 15:19:52 -04:00

Implementation

Differentiates reasons for a read to be four cycles.

2018-06-20 21:34:21 -04:00

Z80.hpp

Removes all instances of the copyright symbol.

2018-05-13 15:19:52 -04:00