Thomas Harte 6e1d69581c Eliminates a variety of end-of-line spaces.

2017-11-07 22:54:22 -05:00

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AllSuiteA

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Atari ROMs

Added a readme, as is traditional for folders I'm excluding from Git.

2017-03-12 22:16:12 -04:00

BCDTest

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Bridges

Corrects 6522 bridge per has-a-not-is-a template switch.

2017-09-04 21:56:21 -04:00

FUSE

After hitting my head against the wall of trying to use [NS]Scanner as a parser some more, have given up and transcoded the two tests files to JSON.

2017-05-25 18:20:13 -04:00

Klaus Dormann

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Wolfgang Lorenz 6502 test suite

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Zexall

Imported the Zexall.com tester, as a first thing to throw at the Z80 to be.

2017-05-16 21:37:09 -04:00

6502InterruptTests.swift

Renamed TestMachine to TestMachine6502 since there's going to be multiple of them.

2017-05-15 08:18:57 -04:00

6502TimingTests.swift

Corrected timestamp return, and its testing by the 6502 timing tests.

2017-07-27 21:19:16 -04:00

6522Tests.swift

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6532Tests.swift

Tested against public ROMs and corrected. Also moved the deferred adjustment into a more canonical place.

2017-03-04 17:00:28 -05:00

AllSuiteATests.swift

Adjusted slightly to adapt to latest Swift warnings.

2017-05-17 07:49:48 -04:00

ArrayBuilderTests.mm

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AtariStaticAnalyserTests.mm

Added an attempt to distinguish the MegaBoy (now with proper capitalisation) and a test for it.

2017-03-13 20:43:12 -04:00

BCDTest.swift

Completed fixture of the 6502 BCD test.

2017-07-25 22:55:45 -04:00

C1540Tests.swift

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CRCTests.mm

Made steps towards proper CRC generation. Am currently comparing against Oric disk images, as — amongst other things — they include precomputed CRCs.

2016-12-28 18:29:37 -05:00

DPLLTests.swift

Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.

2017-07-16 20:55:57 -04:00

FUSETests.swift

Removes usages of deprecated initialiser.

2017-10-05 18:10:47 -04:00

Info.plist

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KlausDormannTests.swift

Adjusted slightly to adapt to latest Swift warnings.

2017-05-17 07:49:48 -04:00

PCMPatchedTrackTests.mm

Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.

2017-08-21 21:56:42 -04:00

PCMSegmentEventSourceTests.mm

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PCMTrackTests.mm

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TIATests.mm

The TIA is now a ClockReceiver.

2017-07-24 21:48:34 -04:00

TimeTests.mm

Added saturation test, fixed code as indicated.

2016-12-24 23:29:37 -05:00

WolfgangLorenzTests.swift

Eliminates a large number of instance of end-of-line tabs.

2017-11-07 22:51:06 -05:00

Z80InterruptTests.swift

Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.

2017-08-23 22:25:31 -04:00

Z80MachineCycleTests.swift

Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.

2017-07-27 20:17:13 -04:00

Z80MemptrTests.swift

Eliminates a variety of end-of-line spaces.

2017-11-07 22:54:22 -05:00

ZexallTests.swift

Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool.

2017-06-04 15:46:35 -04:00