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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00
CLK/OSBindings/Mac/Clock SignalTests
2017-11-07 22:54:22 -05:00
..
AllSuiteA
Atari ROMs
BCDTest
Bridges Corrects 6522 bridge per has-a-not-is-a template switch. 2017-09-04 21:56:21 -04:00
FUSE
Klaus Dormann
Wolfgang Lorenz 6502 test suite
Zexall
6502InterruptTests.swift
6502TimingTests.swift Corrected timestamp return, and its testing by the 6502 timing tests. 2017-07-27 21:19:16 -04:00
6522Tests.swift
6532Tests.swift
AllSuiteATests.swift
ArrayBuilderTests.mm
AtariStaticAnalyserTests.mm
BCDTest.swift Completed fixture of the 6502 BCD test. 2017-07-25 22:55:45 -04:00
C1540Tests.swift
CRCTests.mm
DPLLTests.swift
FUSETests.swift Removes usages of deprecated initialiser. 2017-10-05 18:10:47 -04:00
Info.plist
KlausDormannTests.swift
PCMPatchedTrackTests.mm Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable. 2017-08-21 21:56:42 -04:00
PCMSegmentEventSourceTests.mm
PCMTrackTests.mm
TIATests.mm The TIA is now a ClockReceiver. 2017-07-24 21:48:34 -04:00
TimeTests.mm
WolfgangLorenzTests.swift Eliminates a large number of instance of end-of-line tabs. 2017-11-07 22:51:06 -05:00
Z80InterruptTests.swift Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments. 2017-08-23 22:25:31 -04:00
Z80MachineCycleTests.swift Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests. 2017-07-27 20:17:13 -04:00
Z80MemptrTests.swift Eliminates a variety of end-of-line spaces. 2017-11-07 22:54:22 -05:00
ZexallTests.swift