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435 lines
14 KiB
Plaintext
435 lines
14 KiB
Plaintext
//
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// 68000ArithmeticTests.m
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// Clock SignalTests
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//
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// Created by Thomas Harte on 28/06/2019.
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//
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// Largely ported from the tests of the Portable 68k Emulator.
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//
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#import <XCTest/XCTest.h>
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#include "68000.hpp"
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#include "68000Mk2.hpp"
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#include <array>
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#include <unordered_map>
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#include <set>
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namespace {
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struct RandomStore {
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using CollectionT = std::unordered_map<uint32_t, std::pair<uint8_t, uint8_t>>;
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CollectionT values;
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void flag(uint32_t address, uint8_t participant) {
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values[address].first |= participant;
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}
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bool has(uint32_t address, uint8_t participant) {
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auto entry = values.find(address);
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if(entry == values.end()) return false;
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return entry->second.first & participant;
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}
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uint8_t value(uint32_t address, uint8_t participant) {
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auto entry = values.find(address);
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if(entry != values.end()) {
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entry->second.first |= participant;
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return entry->second.second;
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}
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const uint8_t value = uint8_t(rand() >> 8);
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values[address] = std::make_pair(participant, value);
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return value;
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}
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void clear() {
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values.clear();
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}
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};
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struct Transaction {
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HalfCycles timestamp;
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uint8_t function_code = 0;
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uint32_t address = 0;
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uint16_t value = 0;
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bool address_strobe = false;
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bool read = false;
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int data_strobes = 0;
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bool operator !=(const Transaction &rhs) const {
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if(timestamp != rhs.timestamp) return true;
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// if(function_code != rhs.function_code) return true;
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if(address != rhs.address) return true;
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if(value != rhs.value) return true;
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if(address_strobe != rhs.address_strobe) return true;
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if(data_strobes != rhs.data_strobes) return true;
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return false;
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}
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void print() const {
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printf("%d: %d%d%d %c %c%c @ %06x %s %04x\n",
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timestamp.as<int>(),
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(function_code >> 2) & 1,
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(function_code >> 1) & 1,
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(function_code >> 0) & 1,
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address_strobe ? 'a' : '-',
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(data_strobes & 1) ? 'b' : '-',
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(data_strobes & 2) ? 'w' : '-',
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address,
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read ? "->" : "<-",
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value);
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}
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};
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struct HarmlessStopException {};
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struct BusHandler {
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BusHandler(RandomStore &_store, uint8_t _participant) : store(_store), participant(_participant) {}
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void will_perform(uint32_t, uint16_t) {
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--instructions;
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if(instructions < 0) {
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throw HarmlessStopException{};
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}
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}
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template <typename Microcycle> HalfCycles perform_bus_operation(const Microcycle &cycle, bool is_supervisor) {
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Transaction transaction;
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// Fill all of the transaction record except the data field; will do that after
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// any potential read.
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if(cycle.operation & Microcycle::InterruptAcknowledge) {
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transaction.function_code = 0b111;
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} else {
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transaction.function_code = is_supervisor ? 0x4 : 0x0;
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transaction.function_code |= (cycle.operation & Microcycle::IsData) ? 0x1 : 0x2;
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}
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transaction.address_strobe = cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress);
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transaction.data_strobes = cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord);
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if(cycle.address) transaction.address = *cycle.address & 0xffff'ff;
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transaction.timestamp = time;
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transaction.read = cycle.operation & Microcycle::Read;
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time += cycle.length;
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// Do the operation...
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const uint32_t address = cycle.address ? (*cycle.address & 0xffff'ff) : 0;
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
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default: break;
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case Microcycle::SelectWord | Microcycle::Read:
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if(!store.has(address, participant)) {
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ram[address] = store.value(address, participant);
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}
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if(!store.has(address+1, participant)) {
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ram[address+1] = store.value(address+1, participant);
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}
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cycle.set_value16((ram[address] << 8) | ram[address + 1]);
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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if(!store.has(address, participant)) {
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ram[address] = store.value(address, participant);
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}
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if(address & 1) {
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cycle.set_value8_low(ram[address]);
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} else {
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cycle.set_value8_high(ram[address]);
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}
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break;
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case Microcycle::SelectWord:
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ram[address] = cycle.value8_high();
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ram[address+1] = cycle.value8_low();
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store.flag(address, participant);
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store.flag(address+1, participant);
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break;
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case Microcycle::SelectByte:
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ram[address] = (address & 1) ? cycle.value8_low() : cycle.value8_high();
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store.flag(address, participant);
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break;
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}
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// Add the data value if relevant.
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if(transaction.data_strobes) {
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transaction.value = cycle.value16();
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}
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// Push back only if interesting.
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if(transaction.address_strobe || transaction.data_strobes || transaction.function_code == 7) {
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if(transaction_delay) {
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--transaction_delay;
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// Start counting time only from the first recorded transaction.
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if(!transaction_delay) {
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time = HalfCycles(0);
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}
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} else {
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transactions.push_back(transaction);
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}
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}
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return HalfCycles(0);
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}
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int transaction_delay;
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int instructions;
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HalfCycles time;
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std::vector<Transaction> transactions;
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std::array<uint8_t, 16*1024*1024> ram;
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void set_default_vectors() {
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// Establish that all exception vectors point to 1024-byte blocks of memory.
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for(int c = 0; c < 256; c++) {
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const uint32_t target = (c + 2) << 10;
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const uint32_t address = c << 2;
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ram[address + 0] = uint8_t(target >> 24);
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ram[address + 1] = uint8_t(target >> 16);
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ram[address + 2] = uint8_t(target >> 8);
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ram[address + 3] = uint8_t(target >> 0);
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store.flag(address+0, participant);
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store.flag(address+1, participant);
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store.flag(address+2, participant);
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store.flag(address+3, participant);
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}
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}
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RandomStore &store;
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const uint8_t participant;
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};
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using OldProcessor = CPU::MC68000::Processor<BusHandler, true, true>;
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using NewProcessor = CPU::MC68000Mk2::Processor<BusHandler, true, true, true>;
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template <typename M68000> struct Tester {
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Tester(RandomStore &store, uint8_t participant) : bus_handler(store, participant), processor(bus_handler) {}
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void run_instructions(int instructions) {
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bus_handler.instructions = instructions;
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try {
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processor.run_for(HalfCycles(5000)); // Arbitrary, but will definitely exceed any one instruction (by quite a distance).
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} catch (const HarmlessStopException &) {}
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}
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void reset_with_opcode(uint16_t opcode) {
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bus_handler.transactions.clear();
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bus_handler.set_default_vectors();
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const uint32_t address = 3 << 10;
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bus_handler.ram[address + 0] = uint8_t(opcode >> 8);
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bus_handler.ram[address + 1] = uint8_t(opcode >> 0);
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bus_handler.store.flag(address, bus_handler.participant);
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bus_handler.store.flag(address+1, bus_handler.participant);
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bus_handler.transaction_delay = 12; // i.e. ignore everything from the RESET sequence.
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bus_handler.time = HalfCycles(0);
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processor.reset();
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}
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BusHandler bus_handler;
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M68000 processor;
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};
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}
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@interface M68000OldVsNewTests : XCTestCase
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@end
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@implementation M68000OldVsNewTests
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- (void)testOldVsNew {
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RandomStore random_store;
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auto oldTester = std::make_unique<Tester<OldProcessor>>(random_store, 0x01);
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auto newTester = std::make_unique<Tester<NewProcessor>>(random_store, 0x02);
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InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> decoder;
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// Use a fixed seed to guarantee continuity across repeated runs.
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srand(68000);
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std::set<InstructionSet::M68k::Operation> ignore_list = {
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//
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// Operations that do the wrong thing on the old 68000:
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//
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InstructionSet::M68k::Operation::ABCD, // Old implementation doesn't match flamewing tests, sometimes produces incorrect results.
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InstructionSet::M68k::Operation::SBCD, // Old implementation doesn't match flamewing tests, sometimes produces incorrect results.
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InstructionSet::M68k::Operation::JSR, // Old implementation ends up skipping stack space if the destination throws an address error.
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InstructionSet::M68k::Operation::MOVEtoSR, // Old implementation doesn't repeat a PC fetch.
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InstructionSet::M68k::Operation::MOVEtoCCR, // Old implementation doesn't repeat a PC fetch.
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//
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// Operations with definite timing deficiencies versus Yacht.txt on the old 68000:
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//
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InstructionSet::M68k::Operation::CMPAl, // Old implementation omits an idle cycle before -(An)
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InstructionSet::M68k::Operation::CLRb, // Old implementation omits an idle cycle before -(An)
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InstructionSet::M68k::Operation::CLRw, // Old implementation omits an idle cycle before -(An)
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InstructionSet::M68k::Operation::NEGXb, // Old implementation omits an idle cycle before -(An)
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InstructionSet::M68k::Operation::NEGXw, // Old implementation omits an idle cycle before -(An)
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InstructionSet::M68k::Operation::NEGb, // Old implementation omits an idle cycle before -(An)
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InstructionSet::M68k::Operation::NEGw, // Old implementation omits an idle cycle before -(An)
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InstructionSet::M68k::Operation::NOTb, // Old implementation omits an idle cycle before -(An)
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InstructionSet::M68k::Operation::NOTw, // Old implementation omits an idle cycle before -(An)
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InstructionSet::M68k::Operation::TRAP, // Old implementation relocates the idle state near the end to the beginning.
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InstructionSet::M68k::Operation::TRAPV, // Old implementation relocates the idle state near the end to the beginning.
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InstructionSet::M68k::Operation::CHK, // Old implementation pauses four cycles too long.
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InstructionSet::M68k::Operation::TAS, // Old implementation just doesn't match published cycle counts.
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//
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// Operations with timing discrepancies between the two 68000 implementations
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// that I think are _more_ accurate now, but possibly still need work:
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//
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InstructionSet::M68k::Operation::MULU,
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InstructionSet::M68k::Operation::MULS,
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InstructionSet::M68k::Operation::DIVU,
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InstructionSet::M68k::Operation::DIVS,
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};
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int testsRun = 0;
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std::set<InstructionSet::M68k::Operation> failing_operations;
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for(int c = 0; c < 65536; c++) {
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// printf("%04x\n", c);
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// Test only defined opcodes that aren't STOP (which will never teminate).
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const auto instruction = decoder.decode(uint16_t(c));
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if(
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instruction.operation == InstructionSet::M68k::Operation::Undefined ||
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instruction.operation == InstructionSet::M68k::Operation::STOP
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) {
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continue;
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}
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// If this operation is known to diverge, ignore it. It's dealt with.
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if(ignore_list.find(instruction.operation) != ignore_list.end()) {
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continue;
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}
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// Test each 1000 times.
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for(int test = 0; test < 1000; test++) {
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++testsRun;
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// Establish with certainty the initial memory state.
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random_store.clear();
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newTester->reset_with_opcode(c);
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oldTester->reset_with_opcode(c);
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// Generate a random initial register state.
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auto oldState = oldTester->processor.get_state();
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auto newState = newTester->processor.get_state();
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for(int c = 0; c < 8; c++) {
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oldState.data[c] = newState.registers.data[c] = rand() ^ (rand() << 1);
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if(c != 7) oldState.address[c] = newState.registers.address[c] = rand() << 1;
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}
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// Fully to paper over the two 68000s' different ways of doing a faked
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// reset, pick a random status such that:
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//
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// (i) supervisor mode is active;
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// (ii) trace is inactive; and
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// (iii) interrupt level is 7.
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oldState.status = newState.registers.status = (rand() | (1 << 13) | (7 << 8)) & ~(1 << 15);
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oldState.user_stack_pointer = newState.registers.user_stack_pointer = rand() << 1;
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oldState.supervisor_stack_pointer = newState.registers.supervisor_stack_pointer = 0x800;
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newTester->processor.set_state(newState);
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oldTester->processor.set_state(oldState);
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// Run a single instruction.
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newTester->run_instructions(1);
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oldTester->run_instructions(1);
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// Grab final states.
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oldState = oldTester->processor.get_state();
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newState = newTester->processor.get_state();
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// Compare bus activity only if it doesn't look like an address
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// error occurred. Don't check those as the old 68000 appears to be wrong
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// most of the time about function codes, and that bleeds into the stacked data.
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//
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// Net effect will be 50% fewer transaction comparisons for instructions that
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// can trigger an address error.
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const auto &oldTransactions = oldTester->bus_handler.transactions;
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const auto &newTransactions = newTester->bus_handler.transactions;
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if(oldState.program_counter != 0x1404 || newState.registers.program_counter != 0x1404) {
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auto newIt = newTransactions.begin();
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auto oldIt = oldTransactions.begin();
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while(newIt != newTransactions.end() && oldIt != oldTransactions.end()) {
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if(*newIt != *oldIt) {
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printf("Mismatch in %s, test %d:\n", instruction.to_string().c_str(), test);
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auto repeatIt = newTransactions.begin();
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while(repeatIt != newIt) {
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repeatIt->print();
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++repeatIt;
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}
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printf("---\n");
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while(newIt != newTransactions.end()) {
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printf("n: "); newIt->print();
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++newIt;
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}
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printf("\n");
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while(oldIt != oldTransactions.end()) {
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printf("o: "); oldIt->print();
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++oldIt;
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}
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printf("\n");
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failing_operations.insert(instruction.operation);
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break;
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}
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++newIt;
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++oldIt;
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}
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}
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// Compare registers.
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bool mismatch = false;
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for(int c = 0; c < 8; c++) {
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mismatch |= oldState.data[c] != newState.registers.data[c];
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if(c != 7) mismatch |= oldState.address[c] != newState.registers.address[c];
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}
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mismatch |= oldState.status != newState.registers.status;
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mismatch |= oldState.program_counter != newState.registers.program_counter;
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mismatch |= oldState.user_stack_pointer != newState.registers.user_stack_pointer;
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mismatch |= oldState.supervisor_stack_pointer != newState.registers.supervisor_stack_pointer;
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if(mismatch) {
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failing_operations.insert(instruction.operation);
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printf("Registers don't match after %s, test %d\n", instruction.to_string().c_str(), test);
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for(const auto &transaction: newTransactions) {
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printf("n: "); transaction.print();
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}
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printf("\n");
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for(const auto &transaction: oldTransactions) {
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printf("o: "); transaction.print();
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}
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printf("\n");
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// TODO: more detail here!
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}
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}
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}
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printf("%d tests run\n", testsRun);
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if(failing_operations.empty()) {
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printf("No failures\n");
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} else {
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printf("\nAll failing operations:\n");
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for(const auto operation: failing_operations) {
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printf("%d,\n", int(operation));
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}
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}
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// Mark the test as passed or failed.
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XCTAssert(failing_operations.empty());
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}
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@end
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