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127 lines
3.4 KiB
C++
127 lines
3.4 KiB
C++
//
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// AmstradCPC.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 30/07/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#include "AmstradCPC.hpp"
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using namespace AmstradCPC;
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Machine::Machine() {
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// primary clock is 4Mhz
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set_clock_rate(4000000);
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}
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HalfCycles Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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// Amstrad CPC timing scheme: assert WAIT for three out of four cycles
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clock_offset_ = (clock_offset_ + cycle.length) & HalfCycles(7);
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set_wait_line(clock_offset_ >= HalfCycles(2));
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// Stop now if no action is strictly required.
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if(!cycle.is_terminal()) return HalfCycles(0);
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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case CPU::Z80::PartialMachineCycle::ReadOpcode:
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case CPU::Z80::PartialMachineCycle::Read:
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switch(address >> 14) {
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case 0: *cycle.value = os_[address & 16383]; break;
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case 1: case 2:
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*cycle.value = ram_[address];
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break;
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case 3: *cycle.value = basic_[address & 16383]; break;
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}
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break;
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case CPU::Z80::PartialMachineCycle::Write:
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ram_[address] = *cycle.value;
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break;
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case CPU::Z80::PartialMachineCycle::Output:
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// Check for a gate array access.
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if((address & 0xc000) == 0x4000) {
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switch(*cycle.value >> 6) {
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case 0: printf("Select pen %02x\n", *cycle.value & 0x1f); break;
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case 1: printf("Select colour %02x\n", *cycle.value & 0x1f); break;
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case 2: printf("Set mode %d, other flags %02x\n", *cycle.value & 3, (*cycle.value >> 2)&7); break;
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case 3: printf("RAM paging?\n"); break;
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}
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}
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// Check for a CRTC access
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if(!(address & 0x4000)) {
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switch((address >> 8) & 3) {
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case 0: printf("Select CRTC register %d\n", *cycle.value); break;
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case 1: printf("Set CRTC value %d\n", *cycle.value); break;
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case 2: case 3: printf("Illegal CRTC write?\n"); break;
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}
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}
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// Check for a PIO access
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if(!(address & 0x800)) {
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switch((address >> 8) & 3) {
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case 0: printf("PSG data: %d\n", *cycle.value); break;
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case 1: printf("Vsync, etc: %02x\n", *cycle.value); break;
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case 2: printf("Key row, etc: %02x\n", *cycle.value); break;
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case 3: printf("PIO control: %02x\n", *cycle.value); break;
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}
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}
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// printf("Output %02x -> %04x?\n", *cycle.value, address);
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break;
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case CPU::Z80::PartialMachineCycle::Input:
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printf("Input %04x?\n", address);
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break;
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case CPU::Z80::PartialMachineCycle::Interrupt:
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*cycle.value = 0xff;
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break;
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default: break;
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}
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return HalfCycles(0);
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}
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void Machine::flush() {
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}
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void Machine::set_rom(ROMType type, std::vector<uint8_t> data) {
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// Keep only the two ROMs that are currently of interest.
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switch(type) {
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case ROMType::OS464: os_ = data; break;
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case ROMType::BASIC464: basic_ = data; break;
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default: break;
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}
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}
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void Machine::setup_output(float aspect_ratio) {
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crt_.reset(new Outputs::CRT::CRT(256, 1, Outputs::CRT::DisplayType::PAL50, 1));
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crt_->set_rgb_sampling_function(
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"vec3 rgb_sample(usampler2D sampler, vec2 coordinate, vec2 icoordinate)"
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"{"
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"return vec3(1.0);"
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"}");
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}
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void Machine::close_output() {
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crt_.reset();
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}
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std::shared_ptr<Outputs::CRT::CRT> Machine::get_crt() {
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return crt_;
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}
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std::shared_ptr<Outputs::Speaker> Machine::get_speaker() {
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return nullptr;
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}
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void Machine::run_for(const Cycles cycles) {
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CPU::Z80::Processor<Machine>::run_for(cycles);
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}
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void Machine::configure_as_target(const StaticAnalyser::Target &target) {
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}
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