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271 lines
8.9 KiB
C++
271 lines
8.9 KiB
C++
//
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// Disassembler.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 19/03/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "OperationMapper.hpp"
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#include <string>
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#include <sstream>
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namespace InstructionSet::ARM {
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/// Holds a single ARM operand, whether a source/destination or immediate value, potentially including a shift.
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struct Operand {
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enum class Type {
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Immediate, Register, RegisterList, None
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} type = Type::None;
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uint32_t value = 0;
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// TODO: encode shifting
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operator std::string() const {
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switch(type) {
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default: return "";
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case Type::Register: return std::string("r") + std::to_string(value);
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case Type::RegisterList: {
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std::stringstream stream;
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stream << '[';
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bool first = true;
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for(int c = 0; c < 16; c++) {
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if(value & (1 << c)) {
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if(!first) stream << ", ";
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first = false;
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stream << 'r' << c;
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}
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}
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stream << ']';
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return stream.str();
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}
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}
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}
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};
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/// Describes a single ARM instruction, suboptimally but such that all relevant detail has been extracted
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/// by the OperationMapper and is now easy to inspect or to turn into a string.
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struct Instruction {
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Condition condition = Condition::AL;
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enum class Operation {
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AND, EOR, SUB, RSB,
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ADD, ADC, SBC, RSC,
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TST, TEQ, CMP, CMN,
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ORR, MOV, BIC, MVN,
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LDR, STR,
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LDM, STM,
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B, BL,
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SWI,
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MRC, MCR,
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Undefined,
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} operation = Operation::Undefined;
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Operand destination, operand1, operand2;
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bool sets_flags = false;
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bool is_byte = false;
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std::string to_string(uint32_t address) const {
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std::ostringstream result;
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// Treat all nevers as nops.
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if(condition == Condition::NV) {
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return "nop";
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}
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// Print operation.
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switch(operation) {
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case Operation::Undefined: return "undefined";
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case Operation::SWI: return "swi";
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case Operation::B: result << "b"; break;
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case Operation::BL: result << "bl"; break;
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case Operation::AND: result << "and"; break;
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case Operation::EOR: result << "eor"; break;
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case Operation::SUB: result << "sub"; break;
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case Operation::RSB: result << "rsb"; break;
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case Operation::ADD: result << "add"; break;
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case Operation::ADC: result << "adc"; break;
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case Operation::SBC: result << "sbc"; break;
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case Operation::RSC: result << "rsc"; break;
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case Operation::TST: result << "tst"; break;
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case Operation::TEQ: result << "teq"; break;
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case Operation::CMP: result << "cmp"; break;
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case Operation::CMN: result << "cmn"; break;
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case Operation::ORR: result << "orr"; break;
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case Operation::MOV: result << "mov"; break;
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case Operation::BIC: result << "bic"; break;
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case Operation::MVN: result << "mvn"; break;
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case Operation::LDR: result << "ldr"; break;
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case Operation::STR: result << "str"; break;
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case Operation::LDM: result << "ldm"; break;
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case Operation::STM: result << "stm"; break;
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case Operation::MRC: result << "mrc"; break;
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case Operation::MCR: result << "mcr"; break;
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}
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// Append the sets-flags modifier if applicable.
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if(sets_flags) result << 's';
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// Possibly a condition code.
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switch(condition) {
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case Condition::EQ: result << "eq"; break;
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case Condition::NE: result << "ne"; break;
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case Condition::CS: result << "cs"; break;
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case Condition::CC: result << "cc"; break;
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case Condition::MI: result << "mi"; break;
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case Condition::PL: result << "pl"; break;
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case Condition::VS: result << "vs"; break;
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case Condition::VC: result << "vc"; break;
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case Condition::HI: result << "hi"; break;
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case Condition::LS: result << "ls"; break;
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case Condition::GE: result << "ge"; break;
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case Condition::LT: result << "lt"; break;
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case Condition::GT: result << "gt"; break;
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case Condition::LE: result << "le"; break;
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default: break;
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}
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// If this is a branch, append the target.
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if(operation == Operation::B || operation == Operation::BL) {
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result << " 0x" << std::hex << ((address + 8 + operand1.value) & 0x3fffffc);
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}
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if(
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operation == Operation::LDR || operation == Operation::STR ||
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operation == Operation::LDM || operation == Operation::STM
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) {
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if(is_byte) result << 'b';
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result << ' ' << static_cast<std::string>(destination);
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result << ", [" << static_cast<std::string>(operand1) << "]";
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// TODO: learn how ARM shifts/etc are normally presented.
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}
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return result.str();
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}
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};
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/// A target for @c dispatch that merely captures a description of the decoded instruction, being
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/// able to vend it later via @c last().
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template <Model model>
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struct Disassembler {
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Instruction last() {
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return instruction_;
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}
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bool should_schedule(Condition condition) {
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instruction_ = Instruction();
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instruction_.condition = condition;
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return true;
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}
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template <Flags f> void perform(DataProcessing fields) {
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constexpr DataProcessingFlags flags(f);
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instruction_.operand1.type = Operand::Type::Register;
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instruction_.operand1.value = fields.operand1();
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instruction_.destination.type = Operand::Type::Register;
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instruction_.destination.value = fields.destination();
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if(flags.operand2_is_immediate()) {
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instruction_.operand2.type = Operand::Type::Immediate;
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// instruction_.operand2.value = fields.immediate(), fields.rotate();
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// TODO: decode immediate.
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} else {
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instruction_.operand2.type = Operand::Type::Register;
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instruction_.operand2.value = fields.operand2();
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// TODO: capture shift_type(), etc.
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}
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instruction_.sets_flags = flags.set_condition_codes();
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switch(flags.operation()) {
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case DataProcessingOperation::AND: instruction_.operation = Instruction::Operation::AND; break;
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case DataProcessingOperation::EOR: instruction_.operation = Instruction::Operation::EOR; break;
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case DataProcessingOperation::ORR: instruction_.operation = Instruction::Operation::ORR; break;
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case DataProcessingOperation::BIC: instruction_.operation = Instruction::Operation::BIC; break;
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case DataProcessingOperation::MOV: instruction_.operation = Instruction::Operation::MOV; break;
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case DataProcessingOperation::MVN: instruction_.operation = Instruction::Operation::MVN; break;
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case DataProcessingOperation::TST: instruction_.operation = Instruction::Operation::TST; break;
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case DataProcessingOperation::TEQ: instruction_.operation = Instruction::Operation::TEQ; break;
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case DataProcessingOperation::ADD: instruction_.operation = Instruction::Operation::ADD; break;
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case DataProcessingOperation::ADC: instruction_.operation = Instruction::Operation::ADC; break;
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case DataProcessingOperation::CMN: instruction_.operation = Instruction::Operation::CMN; break;
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case DataProcessingOperation::SUB: instruction_.operation = Instruction::Operation::SUB; break;
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case DataProcessingOperation::SBC: instruction_.operation = Instruction::Operation::SBC; break;
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case DataProcessingOperation::CMP: instruction_.operation = Instruction::Operation::CMP; break;
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case DataProcessingOperation::RSB: instruction_.operation = Instruction::Operation::RSB; break;
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case DataProcessingOperation::RSC: instruction_.operation = Instruction::Operation::RSC; break;
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}
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}
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template <Flags> void perform(Multiply) {}
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template <Flags f> void perform(SingleDataTransfer fields) {
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constexpr SingleDataTransferFlags flags(f);
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instruction_.operation =
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(flags.operation() == SingleDataTransferFlags::Operation::STR) ?
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Instruction::Operation::STR : Instruction::Operation::LDR;
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instruction_.destination.type = Operand::Type::Register;
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instruction_.destination.value = fields.destination();
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instruction_.operand1.type = Operand::Type::Register;
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instruction_.operand1.value = fields.base();
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}
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template <Flags f> void perform(BlockDataTransfer fields) {
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constexpr BlockDataTransferFlags flags(f);
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instruction_.operation =
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(flags.operation() == BlockDataTransferFlags::Operation::STM) ?
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Instruction::Operation::STM : Instruction::Operation::LDM;
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instruction_.destination.type = Operand::Type::Register;
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instruction_.destination.value = fields.base();
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instruction_.operand1.type = Operand::Type::RegisterList;
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instruction_.operand1.value = fields.register_list();
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}
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template <Flags f> void perform(Branch fields) {
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constexpr BranchFlags flags(f);
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instruction_.operation =
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(flags.operation() == BranchFlags::Operation::BL) ?
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Instruction::Operation::BL : Instruction::Operation::B;
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instruction_.operand1.type = Operand::Type::Immediate;
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instruction_.operand1.value = fields.offset();
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}
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template <Flags f> void perform(CoprocessorRegisterTransfer) {
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constexpr CoprocessorRegisterTransferFlags flags(f);
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instruction_.operation =
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(flags.operation() == CoprocessorRegisterTransferFlags::Operation::MRC) ?
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Instruction::Operation::MRC : Instruction::Operation::MCR;
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}
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template <Flags> void perform(CoprocessorDataOperation) {}
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template <Flags> void perform(CoprocessorDataTransfer) {}
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void software_interrupt(SoftwareInterrupt) {
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instruction_.operation = Instruction::Operation::SWI;
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}
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void unknown() {
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instruction_.operation = Instruction::Operation::Undefined;
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}
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private:
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Instruction instruction_;
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};
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}
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