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CLK/Components
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Thomas Harte dc3f8f5e42 These are the three fetchers to implement. 
They'll look fairly different from the TMS and SMS fetchers, I think, owing to the greater irregularity that comes with the smarter RAM accesses. I might need to play around for a while.
2023-01-01 22:44:06 -05:00
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1770
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5380
Continue DMA requests if writing, even after a phase mismatch.
2022-09-15 16:46:22 -04:00
6522
Eliminate unused #includes.
2021-07-18 11:35:57 -04:00
6526
Avoid unnecessary get_port_input calls.
2021-11-24 17:15:48 -05:00
6532
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6560
Switch name back to emphasise _async_.
2022-07-16 14:41:04 -04:00
6845
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6850
Introduce the principle that a Serial::Line can be two-wire — clock + data.
2021-11-06 16:54:20 -07:00
8255
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8272
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8530
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9918
These are the three fetchers to implement.
2023-01-01 22:44:06 -05:00
68901
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AppleClock
Establishes valid initial BRAM.
2021-09-10 19:56:20 -04:00
AudioToggle
Switch name back to emphasise _async_.
2022-07-16 14:41:04 -04:00
AY38910
Switch name back to emphasise _async_.
2022-07-16 14:41:04 -04:00
DiskII
Walk back slightly.
2021-10-14 18:02:58 -07:00
KonamiSCC
Switch name back to emphasise _async_.
2022-07-16 14:41:04 -04:00
OPx
Switch name back to emphasise _async_.
2022-07-16 14:41:04 -04:00
Serial
Add header for assert.
2021-11-24 16:28:18 -05:00
SN76489
Switch name back to emphasise _async_.
2022-07-16 14:41:04 -04:00