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123 lines
3.8 KiB
C++
123 lines
3.8 KiB
C++
//
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// 68000.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 08/03/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#ifndef MC68000_h
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#define MC68000_h
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#include <cstdint>
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#include <iostream>
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#include <vector>
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#include "../../ClockReceiver/ClockReceiver.hpp"
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#include "../RegisterSizes.hpp"
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namespace CPU {
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namespace MC68000 {
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/*!
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A microcycle is an atomic unit of 68000 bus activity — it is a single item large enough
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fully to specify a sequence of bus events that occur without any possible interruption.
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Concretely, a standard read cycle breaks down into at least two microcycles:
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1) a 5 half-cycle length microcycle in which the address strobe is signalled; and
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2) a 3 half-cycle length microcycle in which at least one of the data strobes is
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signalled, and the data bus is sampled.
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That is, assuming DTack were signalled when microcycle (1) ended. If not then additional
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wait state microcycles would fall between those two parts.
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The 68000 data sheet defines when the address becomes valid during microcycle (1), and
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when the address strobe is actually asserted. But those timings are fixed. So simply
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telling you that this was a microcycle during which the address trobe was signalled is
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sufficient fully to describe the bus activity.
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(Aside: see the 68000 template's definition for options re: implicit DTack; if your
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68000 owner can always predict exactly how long it will hold DTack following observation
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of an address-strobing microcycle, it can just supply those periods for accounting and
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avoid the runtime cost of actual DTack emulation. But such as the bus allows.)
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*/
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struct Microcycle {
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/*
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The operation code is a mask of all the signals that relevantly became active during
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this microcycle.
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*/
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static const int Address = 1 << 0;
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static const int UpperData = 1 << 1;
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static const int LowerData = 1 << 2;
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static const int ReadWrite = 1 << 3; // Set = read; unset = write.
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int operation = 0;
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HalfCycles length = HalfCycles(2);
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/*!
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For expediency, this provides a full 32-bit byte-resolution address — e.g.
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if reading indirectly via an address register, this will indicate the full
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value of the address register.
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The receiver should ignore bits 0 and 24+.
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*/
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const uint32_t *address = nullptr;
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RegisterPair16 *value = nullptr;
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};
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/*!
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This is the prototype for a 68000 bus handler; real bus handlers can descend from this
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in order to get default implementations of any changes that may occur in the expected interface.
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*/
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class BusHandler {
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public:
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static const int Data = 1 << 0;
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static const int Program = 1 << 1;
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static const int Supervisor = 1 << 2;
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static const int Interrupt = Data | Program | Supervisor;
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/*!
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Provides the bus handler with a single Microcycle to 'perform', along with the
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contents of the FC0, FC1 and FC2 lines by way of processor_status. The symbols
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above, Data, Program, Supervisor and Interrupt can be used to help to decode the
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processor status if desired; in summary:
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If all three bits are set, this is an interrupt acknowledgement.
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If the data bit is set, the 68000 is fetching data.
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If the program bit is set, the 68000 is fetching instructions.
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It the supervisor bit is set, the 68000 is currently in supervisor mode.
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Neither program nor data being set has an undefined meaning. As does both program
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and data being set, but this not being an interrupt.
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*/
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HalfCycles perform_bus_operation(const Microcycle &cycle, int processor_status) {
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return HalfCycles(0);
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}
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void flush() {}
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};
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#include "Implementation/68000Storage.hpp"
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class ProcessorBase: public ProcessorStorage {
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};
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template <class T> class Processor: public ProcessorBase {
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public:
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void run_for(const Cycles cycles);
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private:
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T &bus_handler_;
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};
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#include "Implementation/68000Implementation.hpp"
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}
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}
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#endif /* MC68000_h */
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