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mirror of https://github.com/TomHarte/CLK.git synced 2024-07-16 22:28:57 +00:00
CLK/OSBindings/Mac/Clock SignalTests
2017-07-24 22:33:49 -04:00
..
AllSuiteA
Atari ROMs
BCDTest
Bridges Corrected test. 2017-07-24 22:33:49 -04:00
FUSE
Klaus Dormann
Wolfgang Lorenz 6502 test suite
Zexall
6502InterruptTests.swift
6502TimingTests.swift
6522Tests.swift
6532Tests.swift
AllSuiteATests.swift
ArrayBuilderTests.mm
AtariStaticAnalyserTests.mm
BCDTest.swift
C1540Tests.swift
CRCTests.mm
DPLLTests.swift Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests. 2017-07-16 20:55:57 -04:00
FUSETests.swift
Info.plist
KlausDormannTests.swift
PCMPatchedTrackTests.mm
PCMSegmentEventSourceTests.mm
PCMTrackTests.mm
TIATests.mm The TIA is now a ClockReceiver. 2017-07-24 21:48:34 -04:00
TimeTests.mm
WolfgangLorenzTests.swift
Z80InterruptTests.swift Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter. 2017-06-22 21:09:26 -04:00
Z80MachineCycleTests.swift Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss. 2017-06-20 22:25:00 -04:00
ZexallTests.swift