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630 lines
23 KiB
C++
630 lines
23 KiB
C++
//
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// MemoryMap.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 25/10/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#ifndef Machines_Apple_AppleIIgs_MemoryMap_hpp
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#define Machines_Apple_AppleIIgs_MemoryMap_hpp
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#include <array>
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#include <vector>
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#include "../AppleII/LanguageCardSwitches.hpp"
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#include "../AppleII/AuxiliaryMemorySwitches.hpp"
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namespace Apple {
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namespace IIgs {
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class MemoryMap {
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public:
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// MARK: - Initial construction and configuration.
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MemoryMap() : auxiliary_switches_(*this), language_card_(*this) {}
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void set_storage(std::vector<uint8_t> &ram, std::vector<uint8_t> &rom) {
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// Keep a pointer for later; also note the proper RAM offset.
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ram_base = ram.data();
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shadow_base[1] = &ram[ram.size() - 0x02'0000]; // i.e. all shadowed writes go somewhere in the last
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// 128bk of RAM.
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// Establish bank mapping.
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uint8_t next_region = 0;
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auto region = [&next_region, this]() -> uint8_t {
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assert(next_region != regions.size());
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return next_region++;
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};
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auto set_region = [this](uint8_t bank, uint16_t start, uint16_t end, uint8_t region) {
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assert((end == 0xffff) || !(end&0xff));
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assert(!(start&0xff));
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// Fill in memory map.
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size_t target = size_t((bank << 8) | (start >> 8));
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for(int c = start; c < end; c += 0x100) {
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region_map[target] = region;
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++target;
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}
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};
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auto set_regions = [this, set_region, region](uint8_t bank, std::initializer_list<uint16_t> addresses, std::vector<uint8_t> allocated_regions = {}) {
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uint16_t previous = 0x0000;
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auto next_region = allocated_regions.begin();
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for(uint16_t address: addresses) {
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set_region(bank, previous, address, next_region != allocated_regions.end() ? *next_region : region());
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previous = address;
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assert(next_region != allocated_regions.end() || allocated_regions.empty());
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if(next_region != allocated_regions.end()) ++next_region;
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}
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assert(next_region == allocated_regions.end());
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};
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// Current beliefs about the IIgs memory map:
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//
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// * language card banking applies to banks $00, $01, $e0 and $e1;
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// * auxiliary memory switches apply to bank $e0 only, but thereby also affect shadowed writes from $00;
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// * shadowing may be enabled only on banks $00 and $01, or on all RAM pages; and
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// * whether bit 16 of the address is passed to the Mega II is selectable — this affects both the destination
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// of odd-bank shadows, and whether bank $e1 is actually distinct from $e0.
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//
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// So:
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//
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// * banks $00 and $01 need to be divided both by shadowing zones and by the language card;
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// * all other fast RAM banks need be divided by shadowing zone only;
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// * $e0 needs to be ready for any language/auxiliary arrangement;
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// * $e1 needs to apply the language card mapping only; and
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// * ROM banks don't need to be divided? Or probably they shadow writes back to $e0/$e1 too?
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// Shadowing zones:
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//
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// $0400–$0800 Text Page 1
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// $0800–$0C00 Text Page 2 [ROM 03 machines]
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// $2000–$4000 High-res Page 1, and Super High-res in odd banks
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// $4000–$6000 High-res Page 2, and Huper High-res in odd banks
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// $6000–$a000 Odd banks only, rest of Super High-res
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// [plus IO and language card space, subject to your definition of shadowing]
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// Language card zones:
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//
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// $D000–$E000 4kb window, into either bank 1 or bank 2
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// $E000–end 12kb window, always the same RAM.
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// Auxiliary zones:
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//
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// $0000–$0200 Zero page (and stack)
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// $0200–$0400 [space in between]
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// $0400–$0800 Text Page 1
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// $0800–$2000 [space in between]
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// $2000–$4000 High-res Page 1
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// $4000–$C000 [space in between]
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// Card zones:
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//
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// $C100–$C2FF either cards or IIe-style ROM
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// $C300–$C3FF IIe-supplied 80-column card replacement ROM
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// $C400–$C7FF either cards or IIe-style ROM
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// $C800–$CFFF Standard extended card area
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// Reserve region 0 as that for unmapped memory.
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region();
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// Bank $00: all locations potentially affected by the auxiliary switches or the
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// language switches. Which will naturally align with shadowable zones.
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set_regions(0x00, {
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0x0200, 0x0400, 0x0800, 0x0c00,
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0x2000, 0x4000, 0x6000,
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0xc000, 0xc100, 0xc300, 0xc400, 0xc800,
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0xd000, 0xe000,
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0xffff
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});
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// Bank $01: all locations potentially affected by the language switches, by shadowing,
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// or marked for IO.
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set_regions(0x01, {
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0x0400, 0x0800, 0x0c00,
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0x2000, 0x4000, 0x6000, 0xa000,
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0xc000, 0xc100, 0xc300, 0xc400, 0xc800,
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0xd000, 0xe000,
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0xffff
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});
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// Banks $02–[end of RAM]: all locations potentially affected by shadowing.
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const uint8_t fast_ram_bank_count = uint8_t((ram.size() - 0x02'0000) / 0x01'0000);
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if(fast_ram_bank_count > 2) {
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const std::vector<uint8_t> evens = {
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region(), // 0x0000 – 0x0400.
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region(), // 0x0400 – 0x0800.
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region(), // 0x0800 – 0x0c00.
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region(), // 0x0c00 – 0x2000.
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region(), // 0x2000 – 0x4000.
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region(), // 0x4000 – 0x6000.
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region(), // 0x6000 – [end].
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};
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const std::vector<uint8_t> odds = {
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region(), // 0x0000 – 0x0400.
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region(), // 0x0400 – 0x0800.
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region(), // 0x0800 – 0x0c00.
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region(), // 0x0c00 – 0x2000.
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region(), // 0x2000 – 0x4000.
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region(), // 0x4000 – 0x6000.
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region(), // 0x6000 – 0xa000.
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region(), // 0xa000 – [end].
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};
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for(uint8_t bank = 0x02; bank < fast_ram_bank_count; bank += 2) {
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set_regions(bank, {0x0400, 0x0800, 0x0c00, 0x2000, 0x4000, 0x6000, 0xffff}, evens);
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set_regions(bank+1, {0x0400, 0x0800, 0x0c00, 0x2000, 0x4000, 0x6000, 0xa000, 0xffff}, odds);
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}
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}
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// [Banks $80–$e0: empty].
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// Banks $e0, $e1: all locations potentially affected by the language switches or marked for IO.
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// Alas, separate regions are needed due to the same ROM appearing on both pages.
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for(uint8_t c = 0; c < 2; c++) {
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set_regions(0xe0 + c, {0xc000, 0xc100, 0xc300, 0xc400, 0xc800, 0xd000, 0xe000, 0xffff});
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}
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// [Banks $e2–[ROM start]: empty].
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// ROM banks: directly mapped to ROM.
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const uint8_t rom_bank_count = uint8_t(rom.size() >> 16);
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const uint8_t first_rom_bank = uint8_t(0x100 - rom_bank_count);
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const uint8_t rom_region = region();
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for(uint8_t c = 0; c < rom_bank_count; ++c) {
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set_region(first_rom_bank + c, 0x0000, 0xffff, rom_region);
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}
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// Apply proper storage to those banks.
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auto set_storage = [this](uint32_t address, const uint8_t *read, uint8_t *write) {
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// Don't allow the reserved null region to be modified.
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assert(region_map[address >> 8]);
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// Either set or apply a quick bit of testing as to the logic at play.
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auto ®ion = regions[region_map[address >> 8]];
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if(read) read -= address;
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if(write) write -= address;
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if(!region.read) {
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region.read = read;
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region.write = write;
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} else {
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assert(region.read == read);
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assert(region.write == write);
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}
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};
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// This is highly redundant, but decouples this step from the above.
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for(size_t c = 0; c < 0x80'0000; c += 0x100) {
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if(c < ram.size() - 0x02'0000) {
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set_storage(uint32_t(c), &ram[c], &ram[c]);
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}
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}
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uint8_t *const slow_ram = &ram[ram.size() - 0x02'0000] - 0xe0'0000;
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for(size_t c = 0xe0'0000; c < 0xe2'0000; c += 0x100) {
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set_storage(uint32_t(c), &slow_ram[c], &slow_ram[c]);
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}
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for(uint32_t c = 0; c < uint32_t(rom_bank_count); c++) {
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set_storage((first_rom_bank + c) << 16, &rom[c << 16], nullptr);
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}
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// TODO: set 1Mhz flags.
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// Apply initial language/auxiliary state.
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set_all_paging();
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}
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// MARK: - Live bus access notifications and register access.
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void set_shadow_register(uint8_t value) {
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const uint8_t diff = value ^ shadow_register_;
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shadow_register_ = value;
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if(diff & 0x40) { // IO/language-card inhibit.
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set_language_card_paging();
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set_card_paging();
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}
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if(diff & 0x3f) {
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set_shadowing();
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}
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}
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uint8_t get_shadow_register() const {
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return shadow_register_;
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}
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void set_speed_register(uint8_t value) {
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const uint8_t diff = value ^ speed_register_;
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speed_register_ = value;
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if(diff & 0x10) {
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set_shadowing();
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}
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}
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void set_state_register(uint8_t value) {
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auxiliary_switches_.set_state(value);
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language_card_.set_state(value);
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}
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uint8_t get_state_register() const {
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return language_card_.get_state() | auxiliary_switches_.get_state();
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}
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void access(uint16_t address, bool is_read) {
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auxiliary_switches_.access(address, is_read);
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if((address & 0xfff0) == 0xc080) language_card_.access(address, is_read);
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}
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using AuxiliaryMemorySwitches = Apple::II::AuxiliaryMemorySwitches<MemoryMap>;
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const AuxiliaryMemorySwitches &auxiliary_switches() const {
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return auxiliary_switches_;
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}
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using LanguageCardSwitches = Apple::II::LanguageCardSwitches<MemoryMap>;
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const LanguageCardSwitches &language_card_switches() const {
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return language_card_;
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}
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private:
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AuxiliaryMemorySwitches auxiliary_switches_;
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LanguageCardSwitches language_card_;
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friend AuxiliaryMemorySwitches;
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friend LanguageCardSwitches;
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uint8_t shadow_register_ = 0x08;
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uint8_t speed_register_ = 0x00;
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// MARK: - Memory banking.
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#define assert_is_region(start, end) \
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assert(region_map[start] == region_map[start-1]+1); \
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assert(region_map[end-1] == region_map[start]); \
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assert(region_map[end] == region_map[end-1]+1);
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// Cf. LanguageCardSwitches; this function should update the region from
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// $D000 onwards as per the state of the language card flags — there may
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// end up being ROM or RAM (or auxiliary RAM), and the first 4kb of it
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// may be drawn from either of two pools.
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void set_language_card_paging() {
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const auto language_state = language_card_.state();
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const auto zero_state = auxiliary_switches_.zero_state();
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const bool inhibit_banks0001 = shadow_register_ & 0x40;
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auto apply = [&language_state, this](uint32_t bank_base, uint8_t *ram) {
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// This assumes bank 1 is the one before bank 2 when RAM is linear.
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uint8_t *const d0_ram_bank = ram - (language_state.bank2 ? 0x0000 : 0x1000);
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// Crib the ROM pointer from a page it's always visible on.
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const uint8_t *const rom = ®ions[region_map[0xffd0]].read[0xff'd000] - ((bank_base << 8) + 0xd000);
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auto &d0_region = regions[region_map[bank_base | 0xd0]];
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d0_region.read = language_state.read ? d0_ram_bank : rom;
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d0_region.write = language_state.write ? nullptr : d0_ram_bank;
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auto &e0_region = regions[region_map[bank_base | 0xe0]];
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e0_region.read = language_state.read ? ram : rom;
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e0_region.write = language_state.write ? nullptr : ram;
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// Assert assumptions made above re: memory layout.
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assert(region_map[bank_base | 0xd0] + 1 == region_map[bank_base | 0xe0]);
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assert(region_map[bank_base | 0xe0] == region_map[bank_base | 0xff]);
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};
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auto set_no_card = [this](uint32_t bank_base) {
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auto &d0_region = regions[region_map[bank_base | 0xd0]];
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d0_region.read = ram_base;
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d0_region.write = ram_base;
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auto &e0_region = regions[region_map[bank_base | 0xe0]];
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e0_region.read = ram_base;
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e0_region.write = ram_base;
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// Assert assumptions made above re: memory layout.
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assert(region_map[bank_base | 0xd0] + 1 == region_map[bank_base | 0xe0]);
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assert(region_map[bank_base | 0xe0] == region_map[bank_base | 0xff]);
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};
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if(inhibit_banks0001) {
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set_no_card(0x0000);
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set_no_card(0x0100);
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} else {
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apply(0x0000, zero_state ? &ram_base[0x01'0000] : ram_base);
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apply(0x0100, ram_base);
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}
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// The pointer stored in region_map[0xe000] has already been adjusted for
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// the 0xe0'0000 addressing offset.
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uint8_t *const e0_ram = regions[region_map[0xe000]].write;
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apply(0xe000, e0_ram);
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apply(0xe100, e0_ram);
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}
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// Cf. AuxiliarySwitches; this should establish whether ROM or card switches
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// are exposed in the distinct regions C100–C2FF, C300–C3FF, C400–C7FF and
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// C800–CFFF.
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//
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// On the IIgs it intersects with the current shadow register.
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//
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// TODO: so... shouldn't the card mask be incorporated here? I've got it implemented
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// distinctly at present, but does that create any invalid state interactions?
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void set_card_paging() {
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const bool inhibit_banks0001 = shadow_register_ & 0x40;
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const auto state = auxiliary_switches_.card_state();
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auto apply = [&state, this](uint32_t bank_base) {
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auto &c0_region = regions[region_map[bank_base | 0xc0]];
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auto &c1_region = regions[region_map[bank_base | 0xc1]];
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auto &c3_region = regions[region_map[bank_base | 0xc3]];
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auto &c4_region = regions[region_map[bank_base | 0xc4]];
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auto &c8_region = regions[region_map[bank_base | 0xc8]];
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const uint8_t *const rom = ®ions[region_map[0xffd0]].read[0xffc100] - ((bank_base << 8) + 0xc100);
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// This is applied dynamically as it may be added or lost in banks $00 and $01.
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c0_region.flags |= Region::IsIO;
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#define apply_region(flag, region) \
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if(flag) { \
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region.read = rom; \
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region.flags &= ~Region::IsIO; \
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} else { \
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region.flags |= Region::IsIO; \
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}
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apply_region(state.region_C1_C3, c1_region);
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apply_region(state.region_C3, c3_region);
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apply_region(state.region_C4_C8, c4_region);
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apply_region(state.region_C8_D0, c8_region);
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#undef apply_region
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// Sanity checks.
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assert(region_map[bank_base | 0xc1] == region_map[bank_base | 0xc0]+1);
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assert(region_map[bank_base | 0xc2] == region_map[bank_base | 0xc1]);
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assert(region_map[bank_base | 0xc3] == region_map[bank_base | 0xc2]+1);
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assert(region_map[bank_base | 0xc4] == region_map[bank_base | 0xc3]+1);
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assert(region_map[bank_base | 0xc7] == region_map[bank_base | 0xc4]);
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assert(region_map[bank_base | 0xc8] == region_map[bank_base | 0xc7]+1);
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assert(region_map[bank_base | 0xcf] == region_map[bank_base | 0xc8]);
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assert(region_map[bank_base | 0xd0] == region_map[bank_base | 0xcf]+1);
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};
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if(inhibit_banks0001) {
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// Set no IO in the Cx00 range for banks $00 and $01, just
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// regular RAM (or possibly auxiliary).
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const auto auxiliary_state = auxiliary_switches_.main_state();
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for(uint8_t region = region_map[0x00c0]; region < region_map[0x00d0]; region++) {
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regions[region].read = auxiliary_state.base.read ? &ram_base[0x01'0000] : ram_base;
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regions[region].write = auxiliary_state.base.write ? &ram_base[0x01'0000] : ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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for(uint8_t region = region_map[0x01c0]; region < region_map[0x01d0]; region++) {
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regions[region].read = regions[region].write = ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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} else {
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// Obey the card state for banks $00 and $01.
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apply(0x0000);
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apply(0x0100);
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}
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// Obey the card state for banks $e0 and $e1.
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apply(0xe000);
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apply(0xe100);
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}
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// Cf. LanguageCardSwitches; this should update whether base or auxiliary RAM is
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// visible in: (i) the zero and stack pages; and (ii) anywhere that the language
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// card is exposing RAM instead of ROM.
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void set_zero_page_paging() {
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// Affects bank $00 only, and should be a single region.
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auto ®ion = regions[region_map[0]];
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region.read = region.write = auxiliary_switches_.zero_state() ? &ram_base[0x01'0000] : ram_base;
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assert(region_map[0x0000] == region_map[0x0001]);
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assert(region_map[0x0001]+1 == region_map[0x0002]);
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// Switching to or from auxiliary RAM potentially affects the
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// language card area.
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set_language_card_paging();
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}
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// IIgs specific: sets or resets the ::IsShadowed flag across affected banks as
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// per the current state of the shadow register.
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//
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// Completely distinct from the auxiliary and language card switches.
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void set_shadowing() {
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||
const bool inhibit_all_pages = !(speed_register_ & 0x10);
|
||
|
||
// Disables shadowing for the region starting from @c zone if @c flag is true;
|
||
// otherwise enables it.
|
||
#define apply(flag, zone) \
|
||
if(flag) { \
|
||
regions[region_map[zone]].flags &= ~Region::IsShadowed; \
|
||
} else { \
|
||
regions[region_map[zone]].flags |= Region::IsShadowed; \
|
||
}
|
||
|
||
// Relevant bits:
|
||
//
|
||
// b5: inhibit shadowing, text page 2 [if ROM 03; as if always set otherwise]
|
||
// b4: inhibit shadowing, auxiliary high-res graphics
|
||
// b3: inhibit shadowing, super high-res graphics
|
||
// b2: inhibit shadowing, high-res graphics page 2
|
||
// b1: inhibit shadowing, high-res graphics page 1
|
||
// b0: inhibit shadowing, text page 1
|
||
//
|
||
// The interpretations of how the overlapping high-res and super high-res inhibit
|
||
// bits apply used below is taken from The Apple IIgs Technical Reference, P. 178.
|
||
|
||
// Text Page 1, main and auxiliary — $0400–$0800.
|
||
apply(shadow_register_ & 0x01, 0x0004);
|
||
apply(shadow_register_ & 0x01, 0x0104);
|
||
apply((shadow_register_ & 0x01) || inhibit_all_pages, 0x0204); // All other pages uses the same shadowing flags.
|
||
apply((shadow_register_ & 0x01) || inhibit_all_pages, 0x0304);
|
||
assert_is_region(0x004, 0x008);
|
||
assert_is_region(0x104, 0x108);
|
||
assert_is_region(0x204, 0x208);
|
||
assert_is_region(0x304, 0x308);
|
||
|
||
// Text Page 2, main and auxiliary — 0x0800–0x0c00.
|
||
// TODO: on a ROM03 machine only.
|
||
apply(shadow_register_ & 0x20, 0x0008);
|
||
apply(shadow_register_ & 0x20, 0x0108);
|
||
apply((shadow_register_ & 0x20) || inhibit_all_pages, 0x0208);
|
||
apply((shadow_register_ & 0x20) || inhibit_all_pages, 0x0308);
|
||
assert_is_region(0x008, 0x00c);
|
||
assert_is_region(0x108, 0x10c);
|
||
assert_is_region(0x208, 0x20c);
|
||
assert_is_region(0x308, 0x30c);
|
||
|
||
// Hi-res graphics Page 1, main and auxiliary — $2000–$4000;
|
||
// also part of the super high-res graphics page on odd pages.
|
||
//
|
||
// Even test applied:
|
||
// high-res graphics page 1 inhibit bit alone is definitive.
|
||
//
|
||
// Odd test:
|
||
// (high-res graphics inhibit or auxiliary high res graphics inhibit) _and_ (super high-res inhibit).
|
||
//
|
||
apply(shadow_register_ & 0x02, 0x0020);
|
||
apply((shadow_register_ & 0x12) && (shadow_register_ & 0x08), 0x0120);
|
||
apply((shadow_register_ & 0x02) || inhibit_all_pages, 0x0220);
|
||
apply(((shadow_register_ & 0x12) && (shadow_register_ & 0x08)) || inhibit_all_pages, 0x0320);
|
||
assert_is_region(0x020, 0x040);
|
||
assert_is_region(0x120, 0x140);
|
||
assert_is_region(0x220, 0x240);
|
||
assert_is_region(0x320, 0x340);
|
||
|
||
// Hi-res graphics Page 2, main and auxiliary — $4000–$6000;
|
||
// also part of the super high-res graphics page.
|
||
//
|
||
// Test applied: much like that for page 1.
|
||
apply(shadow_register_ & 0x04, 0x0040);
|
||
apply((shadow_register_ & 0x14) && (shadow_register_ & 0x08), 0x0140);
|
||
apply((shadow_register_ & 0x04) || inhibit_all_pages, 0x0240);
|
||
apply(((shadow_register_ & 0x14) && (shadow_register_ & 0x08)) || inhibit_all_pages, 0x0340);
|
||
assert_is_region(0x040, 0x060);
|
||
assert_is_region(0x140, 0x160);
|
||
assert_is_region(0x240, 0x260);
|
||
assert_is_region(0x340, 0x360);
|
||
|
||
// Residue of Super Hi-Res — $6000–$a000 (odd pages only).
|
||
apply(shadow_register_ & 0x08, 0x0160);
|
||
apply((shadow_register_ & 0x08) || inhibit_all_pages, 0x0360);
|
||
assert_is_region(0x160, 0x1a0);
|
||
assert_is_region(0x360, 0x3a0);
|
||
|
||
#undef apply
|
||
}
|
||
|
||
// Cf. the AuxiliarySwitches; establishes whether main or auxiliary RAM
|
||
// is exposed in bank $00 for a bunch of regions.
|
||
void set_main_paging() {
|
||
const auto state = auxiliary_switches_.main_state();
|
||
|
||
#define set(page, flags) {\
|
||
auto ®ion = regions[region_map[page]]; \
|
||
region.read = flags.read ? &ram_base[0x01'0000] : ram_base; \
|
||
region.write = flags.write ? &ram_base[0x01'0000] : ram_base; \
|
||
}
|
||
|
||
// Base: $0200–$03FF.
|
||
set(0x02, state.base);
|
||
assert_is_region(0x02, 0x04);
|
||
|
||
// Region $0400–$07ff.
|
||
set(0x04, state.region_04_08);
|
||
assert_is_region(0x04, 0x08);
|
||
|
||
// Base: $0800–$1FFF.
|
||
set(0x08, state.base);
|
||
set(0x0c, state.base);
|
||
assert_is_region(0x08, 0x0c);
|
||
assert_is_region(0x0c, 0x20);
|
||
|
||
// Region $2000–$3FFF.
|
||
set(0x20, state.region_20_40);
|
||
assert_is_region(0x20, 0x40);
|
||
|
||
// Base: $4000–$BFFF.
|
||
set(0x40, state.base);
|
||
set(0x60, state.base);
|
||
assert_is_region(0x40, 0x60);
|
||
assert_is_region(0x60, 0xc0);
|
||
|
||
#undef set
|
||
|
||
// This also affects shadowing flags, if shadowing is enabled at all,
|
||
// and might affect RAM in the IO area of bank $00 because the language
|
||
// card can be inhibited on a IIgs.
|
||
set_card_paging();
|
||
}
|
||
|
||
void set_all_paging() {
|
||
set_card_paging();
|
||
set_zero_page_paging(); // ... which calls set_language_card_paging().
|
||
set_main_paging();
|
||
set_shadowing();
|
||
}
|
||
|
||
// Throwaway storage to facilitate branchless handling of shadowing.
|
||
uint8_t shadow_throwaway_;
|
||
|
||
#undef assert_is_region
|
||
|
||
public:
|
||
// Memory layout here is done via double indirection; the main loop should:
|
||
// (i) use the top two bytes of the address to get an index from memory_map_; and
|
||
// (ii) use that to index the memory_regions table.
|
||
//
|
||
// Pointers are eight bytes at the time of writing, so the extra level of indirection
|
||
// reduces what would otherwise be a 1.25mb table down to not a great deal more than 64kb.
|
||
std::array<uint8_t, 65536> region_map{};
|
||
uint8_t *ram_base = nullptr;
|
||
uint8_t *shadow_base[2] = {&shadow_throwaway_, nullptr};
|
||
static constexpr int shadow_mask[2] = {0, 0x01'ffff};
|
||
|
||
struct Region {
|
||
uint8_t *write = nullptr;
|
||
const uint8_t *read = nullptr;
|
||
uint8_t flags = 0;
|
||
|
||
enum Flag: uint8_t {
|
||
IsShadowed = 1 << 0, // Writes should be shadowed to [end of RAM - 128kb + base offset].
|
||
Is1Mhz = 1 << 1, // Both reads and writes should be synchronised with the 1Mhz clock.
|
||
IsIO = 1 << 2, // Indicates that this region should be checked for soft switches, registers, etc;
|
||
// usurps the shadowed flags.
|
||
};
|
||
};
|
||
std::array<Region, 64> regions; // The assert above ensures that this is large enough; there's no
|
||
// doctrinal reason for it to be whatever size it is now, just
|
||
// adjust as required.
|
||
};
|
||
|
||
// TODO: branching below on region.read/write is predicated on the idea that extra scratch space
|
||
// would be less efficient. Verify that?
|
||
|
||
#define MemoryMapRegion(map, address) map.regions[map.region_map[address >> 8]]
|
||
#define MemoryMapRead(region, address, value) *value = region.read ? region.read[address] : 0xff
|
||
#define MemoryMapWrite(map, region, address, value) \
|
||
if(region.write) { \
|
||
region.write[address] = *value; \
|
||
const bool is_shadowed = region.flags & MemoryMap::Region::IsShadowed; \
|
||
map.shadow_base[is_shadowed][(®ion.write[address] - map.ram_base) & map.shadow_mask[is_shadowed]] = *value; \
|
||
}
|
||
|
||
// Quick notes on ::IsShadowed contortions:
|
||
//
|
||
// The objective is to support shadowing:
|
||
// 1. without storing a whole extra pointer, and such that the shadowing flags are orthogonal to the current auxiliary memory settings;
|
||
// 2. in such a way as to support shadowing both in banks $00/$01 and elsewhere; and
|
||
// 3. to do so without introducing too much in the way of branching.
|
||
//
|
||
// Hence the implemented solution: if shadowing is enabled then use the distance from the start of physical RAM
|
||
// modulo 128k indexed into the bank $e0/$e1 RAM.
|
||
//
|
||
// With a further twist: the modulo and pointer are indexed on ::IsShadowed to eliminate a branch even on that.
|
||
|
||
}
|
||
}
|
||
|
||
#endif /* MemoryMap_h */
|