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261 lines
7.9 KiB
C++
261 lines
7.9 KiB
C++
//
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// Enterprise.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/06/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#include "Enterprise.hpp"
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#include "Nick.hpp"
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#include "../MachineTypes.hpp"
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#include "../../Processors/Z80/Z80.hpp"
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#include "../../Analyser/Static/Enterprise/Target.hpp"
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#include "../../ClockReceiver/JustInTime.hpp"
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namespace Enterprise {
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/*
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Notes to self on timing:
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Nick divides each line into 57 windows; each window lasts 16 cycles and dedicates the
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first 10 of those to VRAM accesses, leaving the final six for a Z80 video RAM access
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if one has been requested.
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The Z80 has a separate, asynchronous 4Mhz clock. That's that.
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The documentation is also very forward in emphasising that Nick generates phaselocked
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(i.e. in-phase) PAL video.
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So: 57*16 = 912 cycles/line.
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A standard PAL line lasts 64µs and during that time outputs 283.7516 colour cycles.
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I shall _guess_ that the Enterprise stretches each line to 284 colour cycles rather than
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reducing it to 283.
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Therefore 912 cycles occurs in 284/283.7516 * 64 µs, which would appear to give an ideal
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clock rate of around:
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14,237,536.27 Hz.
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Given that there's always some leeway in a receiver, I'm modelling that as 14,237,536 cycles,
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which means that Nick runs 444923/125000 times as fast as the Z80. Which is around 3.56 times
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as fast.
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If that's true then the 6-cycle window is around 1.69 Z80 cycles long. Given that the Z80
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clock in an Enterprise can be stopped in half-cycle increments only, the Z80 can only be
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guaranteed to have around a 1.19 cycle minimum for its actual access. I'm therefore further
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postulating that the clock stoppage takes place so as to align the final cycle of a relevant
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access over the available window.
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*/
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class ConcreteMachine:
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public CPU::Z80::BusHandler,
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public Machine,
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public MachineTypes::ScanProducer,
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public MachineTypes::TimedMachine {
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public:
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ConcreteMachine([[maybe_unused]] const Analyser::Static::Enterprise::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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z80_(*this),
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nick_(ram_.end() - 65536) {
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// Request a clock of 4Mhz; this'll be mapped upwards for Nick and Dave elsewhere.
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set_clock_rate(4'000'000);
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constexpr ROM::Name exos_name = ROM::Name::EnterpriseEXOS;
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const auto request = ROM::Request(exos_name);
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auto roms = rom_fetcher(request);
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if(!request.validate(roms)) {
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throw ROMMachine::Error::MissingROMs;
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}
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const auto &exos = roms.find(exos_name)->second;
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memcpy(exos_.data(), exos.data(), std::min(exos_.size(), exos.size()));
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// Take a reasonable guess at the initial memory configuration:
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// put EXOS into the first bank since this is a Z80 and therefore
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// starts from address 0; the third instruction in EXOS is a jump
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// to $c02e so it's reasonable to assume EXOS is in the highest bank
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// too, and it appears to act correctly if it's the first 16kb that's
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// in the highest bank. From there I guess: all banks are initialised
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// to 0.
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page<0>(0x00);
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page<1>(0x00);
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page<2>(0x00);
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page<3>(0x00);
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}
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// MARK: - Z80::BusHandler.
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forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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using PartialMachineCycle = CPU::Z80::PartialMachineCycle;
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const uint16_t address = cycle.address ? *cycle.address : 0x0000;
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// TODO: possibly apply an access penalty.
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nick_ += cycle.length;
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switch(cycle.operation) {
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default: break;
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case CPU::Z80::PartialMachineCycle::Input:
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switch(address & 0xff) {
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default:
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printf("Unhandled input: %04x\n", address);
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assert(false);
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break;
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case 0xb0: *cycle.value = pages_[0]; break;
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case 0xb1: *cycle.value = pages_[1]; break;
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case 0xb2: *cycle.value = pages_[2]; break;
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case 0xb3: *cycle.value = pages_[3]; break;
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case 0xb4:
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printf("TODO: interrupt enable/reset read\n");
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*cycle.value = 0xff;
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break;
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case 0xb5:
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printf("TODO: Keyboard/joystick input\n");
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*cycle.value = 0xff;
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break;
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}
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break;
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case CPU::Z80::PartialMachineCycle::Output:
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switch(address & 0xff) {
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default:
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printf("Unhandled output: %04x\n", address);
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assert(false);
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break;
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case 0x80: case 0x81: case 0x82: case 0x83:
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case 0x84: case 0x85: case 0x86: case 0x87:
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case 0x88: case 0x89: case 0x8a: case 0x8b:
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case 0x8c: case 0x8d: case 0x8e: case 0x8f:
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nick_->write(address, *cycle.value);
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break;
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case 0xb0: page<0>(*cycle.value); break;
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case 0xb1: page<1>(*cycle.value); break;
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case 0xb2: page<2>(*cycle.value); break;
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case 0xb3: page<3>(*cycle.value); break;
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case 0xa0: case 0xa1: case 0xa2: case 0xa3:
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case 0xa4: case 0xa5: case 0xa6: case 0xa7:
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case 0xa8: case 0xa9: case 0xaa: case 0xab:
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case 0xac: case 0xad: case 0xae: case 0xaf:
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printf("TODO: audio adjust %04x <- %02x\n", address, *cycle.value);
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break;
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case 0xb4:
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printf("TODO: interrupt enable/reset write %02x\n", *cycle.value);
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break;
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case 0xb5:
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printf("TODO: Keyboard/etc %02x\n", *cycle.value);
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break;
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case 0xb6:
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printf("TODO: printer output %02x\n", *cycle.value);
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break;
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case 0xbf:
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printf("TODO: Dave sysconfig %02x\n", *cycle.value);
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break;
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}
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break;
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case CPU::Z80::PartialMachineCycle::Read:
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case CPU::Z80::PartialMachineCycle::ReadOpcode:
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if(read_pointers_[address >> 14]) {
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*cycle.value = read_pointers_[address >> 14][address];
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} else {
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*cycle.value = 0xff;
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}
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break;
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case CPU::Z80::PartialMachineCycle::Write:
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if(write_pointers_[address >> 14]) {
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write_pointers_[address >> 14][address] = *cycle.value;
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}
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break;
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}
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return HalfCycles(0);
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}
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void flush() {
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nick_.flush();
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}
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private:
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// MARK: - Memory layout
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std::array<uint8_t, 256 * 1024> ram_;
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std::array<uint8_t, 32 * 1024> exos_;
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const uint8_t min_ram_slot_ = 0xff - 3;
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const uint8_t *read_pointers_[4] = {nullptr, nullptr, nullptr, nullptr};
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uint8_t *write_pointers_[4] = {nullptr, nullptr, nullptr, nullptr};
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uint8_t pages_[4] = {0x80, 0x80, 0x80, 0x80};
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template <size_t slot> void page(uint8_t offset) {
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pages_[slot] = offset;
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if(offset < 2) {
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page<slot>(&exos_[offset * 0x4000], nullptr);
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return;
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}
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// Of whatever size of RAM I've declared above, use only the final portion.
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// This correlated with Nick always having been handed the final 64kb and,
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// at least while the RAM is the first thing declared above, does a little
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// to benefit data locality. Albeit not in a useful sense.
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if(offset >= min_ram_slot_) {
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const auto ram_floor = 4194304 - ram_.size();
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const size_t address = offset * 0x4000 - ram_floor;
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page<slot>(&ram_[address], &ram_[address]);
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return;
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}
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page<slot>(nullptr, nullptr);
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}
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template <size_t slot> void page(const uint8_t *read, uint8_t *write) {
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read_pointers_[slot] = read ? read - (slot * 0x4000) : nullptr;
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write_pointers_[slot] = write ? write - (slot * 0x4000) : nullptr;
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}
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// MARK: - ScanProducer
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void set_scan_target(Outputs::Display::ScanTarget *scan_target) override {
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nick_.last_valid()->set_scan_target(scan_target);
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}
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Outputs::Display::ScanStatus get_scaled_scan_status() const override {
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return nick_.last_valid()->get_scaled_scan_status();
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}
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// MARK: - TimedMachine
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void run_for(const Cycles cycles) override {
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z80_.run_for(cycles);
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}
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// MARK: - Chips.
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CPU::Z80::Processor<ConcreteMachine, false, false> z80_;
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JustInTimeActor<Nick, HalfCycles, 444923, 125000> nick_;
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// Cf. timing guesses above.
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};
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}
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using namespace Enterprise;
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Machine *Machine::Enterprise(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
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using Target = Analyser::Static::Enterprise::Target;
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const Target *const enterprise_target = dynamic_cast<const Target *>(target);
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return new Enterprise::ConcreteMachine(*enterprise_target, rom_fetcher);
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}
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Machine::~Machine() {}
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