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498 lines
16 KiB
C++
498 lines
16 KiB
C++
//
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// Z80.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 14/05/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#ifndef Z80_hpp
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#define Z80_hpp
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#include <cstdint>
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#include <cstdio>
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#include "../MicroOpScheduler.hpp"
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#include "../RegisterSizes.hpp"
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namespace CPU {
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namespace Z80 {
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/*
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The list of registers that can be accessed via @c set_value_of_register and @c set_value_of_register.
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*/
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enum Register {
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ProgramCounter,
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StackPointer,
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A, Flags, AF,
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B, C, BC,
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D, E, DE,
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H, L, HL,
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ADash, FlagsDash, AFDash,
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BDash, CDash, BCDash,
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DDash, EDash, DEDash,
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HDash, LDash, HLDash,
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IXh, IXl, IX,
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IYh, IYl, IY,
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R, I,
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};
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/*
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Flags as defined on the Z80; can be used to decode the result of @c get_flags or to form a value for @c set_flags.
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*/
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enum Flag: uint8_t {
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Sign = 0x80,
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Zero = 0x40,
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Bit5 = 0x20,
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HalfCarry = 0x10,
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Bit3 = 0x08,
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Parity = 0x04,
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Overflow = 0x04,
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Subtract = 0x02,
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Carry = 0x01
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};
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/*!
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Subclasses will be given the task of performing bus operations, allowing them to provide whatever interface they like
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between a Z80 and the rest of the system. @c BusOperation lists the types of bus operation that may be requested.
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@c None is reserved for internal use. It will never be requested from a subclass.
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*/
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enum BusOperation {
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ReadOpcode = 0,
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Read, Write,
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Input, Output,
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Interrupt,
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// BusRequest, BusAcknowledge,
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Internal
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};
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struct MachineCycle {
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const BusOperation operation;
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const int length;
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const uint16_t *address;
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uint8_t *const value;
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};
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struct MicroOp {
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enum {
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BusOperation,
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DecodeOperation,
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MoveToNextProgram,
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Increment16,
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Decrement16,
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Move8,
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Move16,
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AssembleAF,
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None
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} type;
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void *source;
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void *destination;
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MachineCycle machine_cycle;
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};
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/*!
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@abstact An abstract base class for emulation of a 6502 processor via the curiously recurring template pattern/f-bounded polymorphism.
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@discussion Subclasses should implement @c perform_bus_operation(BusOperation operation, uint16_t address, uint8_t *value) in
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order to provide the bus on which the 6502 operates and @c flush(), which is called upon completion of a continuous run
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of cycles to allow a subclass to bring any on-demand activities up to date.
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Additional functionality can be provided by the host machine by providing a jam handler and inserting jam opcodes where appropriate;
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that will cause call outs when the program counter reaches those addresses. @c return_from_subroutine can be used to exit from a
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jammed state.
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*/
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template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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private:
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uint8_t a_, i_, r_;
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RegisterPair bc_, de_, hl_;
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RegisterPair afDash_, bcDash_, deDash_, hlDash_;
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RegisterPair ix_, iy_, pc_, sp_;
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uint8_t carry_flag_, sign_result_, bit5_result_, half_carry_flag_, bit3_result_, parity_overflow_flag_, subtract_flag_;
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int number_of_cycles_;
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const MicroOp **program_table_;
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uint8_t operation_;
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RegisterPair address_, temporary_;
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void decode_base_operation(uint8_t operation) {
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#define XX {MicroOp::None, 0}
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#define FETCH(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Read, 3, &y.full, &x}}, {MicroOp::Increment16, &y.full}
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#define FETCHL(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Read, 3, &y.full, &x}}
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#define STOREL(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Write, 3, &y.full, &x}}
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#define FETCH16(x, y) FETCH(x.bytes.low, y), FETCH(x.bytes.high, y)
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#define FETCH16L(x, y) FETCH(x.bytes.low, y), FETCHL(x.bytes.high, y)
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#define PUSH(x) STOREL(x.bytes.high, sp_), {MicroOp::Decrement16, &sp_.full}, STOREL(x.bytes.low, sp_), {MicroOp::Decrement16, &sp_.full}
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#define WAIT(n) {MicroOp::BusOperation, nullptr, nullptr, {Internal, n} }
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#define Program(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} }
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static const MicroOp base_program_table[256][20] = {
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{ {MicroOp::MoveToNextProgram} }, /* 0x00 NOP */
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Program(FETCH16(bc_, pc_)), /* 0x01 LD BC, nn */
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XX, /* 0x02 LD (BC), A */
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XX, /* 0x03 INC BC */
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XX, /* 0x04 INC B */
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XX, /* 0x05 DEC B */
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Program(FETCH(bc_.bytes.high, pc_)), /* 0x06 LD B, n */
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XX, /* 0x07 RLCA */
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XX, /* 0x08 EX AF, AF' */
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XX, /* 0x09 ADD HL, BC */
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XX, /* 0x0a LD A, (BC) */
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XX, /* 0x0b DEC BC */
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XX, /* 0x0c INC C */
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XX, /* 0x0d DEC C */
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Program(FETCH(bc_.bytes.low, pc_)), /* 0x0e LD C, n */
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XX, /* 0x0f RRCA */
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XX, /* 0x10 DJNZ */
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Program(FETCH16(de_, pc_)), /* 0x11 LD DE, nn */
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XX, /* 0x12 LD (DE), A */
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XX, /* 0x13 INC DE */
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XX, /* 0x14 INC D */
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XX, /* 0x15 DEC D */
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Program(FETCH(de_.bytes.high, pc_)), /* 0x16 LD D, n */
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XX, /* 0x17 RLA */
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XX, /* 0x18 JR */
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XX, /* 0x19 ADD HL, DE */
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XX, /* 0x1a LD A, (DE) */
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XX, /* 0x1b DEC DE */
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XX, /* 0x1c INC E */
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XX, /* 0x1d DEC E */
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Program(FETCH(de_.bytes.low, pc_)), /* 0x1e LD E, n */
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XX, /* 0x1f RRA */
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XX, /* 0x20 JR NZ */
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Program(FETCH16(hl_, pc_)), /* 0x21 LD HL, nn */
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XX, /* 0x22 LD (nn), HL */
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XX, /* 0x23 INC HL */
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XX, /* 0x24 INC H */
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XX, /* 0x25 DEC H */
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Program(FETCH(hl_.bytes.high, pc_)), /* 0x26 LD H, n */
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XX, /* 0x27 DAA */
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XX, /* 0x28 JR Z */
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XX, /* 0x29 ADD HL, HL */
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Program(FETCH16(address_, pc_), FETCH16L(hl_, address_)), /* 0x2a LD HL, (nn) */
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XX, /* 0x2b DEC HL */
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XX, /* 0x2c INC L */
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XX, /* 0x2d DEC L */
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Program(FETCH(hl_.bytes.low, pc_)), /* 0x2e LD L, n */
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XX, /* 0x2f CPL */
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XX, /* 0x30 JR NC */
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Program(FETCH16(sp_, pc_)), /* 0x31 LD SP, nn */
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XX, /* 0x32 LD (nn), A */
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XX, /* 0x33 INC SP */
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XX, /* 0x34 INC (HL) */
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XX, /* 0x35 DEC (HL) */
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XX, /* 0x36 LD (HL), n */
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XX, /* 0x37 SCF */
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x38
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x40
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x48
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x50
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x58
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x60
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x68
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x70
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x78
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x80
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x88
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x90
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x98
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xa0
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xa8
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xb0
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xb8
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XX, /* 0xc0 RET NZ */
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XX, /* 0xc1 POP BC */
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XX, /* 0xc2 JP NZ */
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Program(FETCH16L(address_, pc_), {MicroOp::Move16, &address_.full, &pc_.full}), /* 0xc3 JP nn */
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XX, /* 0xc4 CALL NZ */
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Program(WAIT(2), PUSH(bc_)), /* 0xc5 PUSH BC */
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XX, /* 0xc6 ADD A, n */
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XX, /* 0xc7 RST 00h */
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XX, /* 0xc8 RET Z */
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XX, /* 0xc9 RET */
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XX, /* 0xca JP Z */
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XX, /* 0xcb [CB page] */
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XX, /* 0xcc CALL Z */
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Program(FETCH16(address_, pc_), WAIT(1), PUSH(pc_), {MicroOp::Move16, &address_.full, &pc_.full}), /* 0xcd CALL */
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XX, /* 0xce ADC A, n */
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XX, /* 0xcf RST 08h */
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XX, /* 0xd0 RET NC */
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XX, /* 0xd1 POP DE */
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XX, /* 0xd2 JP NC */
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XX, /* 0xd3 OUT (n), A */
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XX, /* 0xd4 CALL NC */
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Program(WAIT(2), PUSH(de_)), /* 0xd5 PUSH DE */
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XX, /* 0xd6 SUB n */
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XX, /* 0xd7 RST 10h */
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xd8
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XX, /* 0xe0 RET PO */
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XX, /* 0xe1 POP HL */
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XX, /* 0xe2 JP PO */
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XX, /* 0xe3 EX (SP), HL */
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XX, /* 0xe4 CALL PO */
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Program(WAIT(2), PUSH(hl_)), /* 0xe5 PUSH HL */
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XX, /* 0xe6 AND n */
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XX, /* 0xe7 RST 20h */
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xe8
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XX, /* 0xf0 RET p */
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XX, /* 0xf1 POP AF */
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XX, /* 0xf2 JP P */
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XX, /* 0xf3 DI */
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XX, /* 0xf4 CALL P */
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Program(WAIT(2), {MicroOp::AssembleAF}, PUSH(temporary_)), /* 0xf5 PUSH AF */
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XX, /* 0xf6 OR n */
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XX, /* 0xf7 RST 30h */
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XX, /* 0xf8 RET M */
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Program(WAIT(2), {MicroOp::Move16, &hl_.full, &sp_.full}), /* 0xf9 LD SP, HL */
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XX, /* 0xfa JP M */
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XX, /* 0xfb EI */
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XX, /* 0xfc CALL M */
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XX, /* 0xfd [FD page] */
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XX, /* 0xfe CP n */
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XX, /* 0xff RST 38h */
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};
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if(base_program_table[operation][0].type == MicroOp::None) {
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printf("Unknown Z80 operation %02x!!!\n", operation);
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}
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schedule_program(base_program_table[operation]);
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// program_table_ = base_program_table;
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}
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public:
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Processor() {
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// set_base_program_table();
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}
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/*!
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Runs the Z80 for a supplied number of cycles.
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@discussion Subclasses must implement @c perform_machine_cycle(MachineCycle *cycle) .
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If it is a read operation then @c value will be seeded with the value 0xff.
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@param number_of_cycles The number of cycles to run the Z80 for.
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*/
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void run_for_cycles(int number_of_cycles) {
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static const MicroOp fetch_decode_execute[] = {
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{ MicroOp::BusOperation, nullptr, nullptr, {ReadOpcode, 4, &pc_.full, &operation_}},
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{ MicroOp::DecodeOperation },
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{ MicroOp::MoveToNextProgram }
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};
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#define checkSchedule() \
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if(!scheduled_programs_[schedule_programs_read_pointer_]) {\
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schedule_program(fetch_decode_execute);\
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}
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number_of_cycles_ += number_of_cycles;
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checkSchedule();
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while(1) {
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const MicroOp *operation = &scheduled_programs_[schedule_programs_read_pointer_][schedule_program_program_counter_];
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schedule_program_program_counter_++;
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switch(operation->type) {
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case MicroOp::BusOperation:
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if(number_of_cycles_ < operation->machine_cycle.length) {
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return;
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}
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static_cast<T *>(this)->perform_machine_cycle(&operation->machine_cycle);
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break;
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case MicroOp::MoveToNextProgram:
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move_to_next_program();
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checkSchedule();
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break;
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case MicroOp::DecodeOperation:
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pc_.full++;
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decode_base_operation(operation_);
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break;
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case MicroOp::Increment16: (*(uint16_t *)operation->source)++; break;
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case MicroOp::Decrement16: (*(uint16_t *)operation->source)--; break;
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case MicroOp::Move8: *(uint8_t *)operation->destination = *(uint8_t *)operation->source; break;
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case MicroOp::Move16: *(uint16_t *)operation->destination = *(uint16_t *)operation->source; break;
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case MicroOp::AssembleAF:
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temporary_.bytes.high = a_;
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temporary_.bytes.low = get_flags();
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break;
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default:
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printf("Unhandled Z80 operation %d\n", operation->type);
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return;
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}
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}
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}
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/*!
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Called to announce the end of a run_for_cycles period, allowing deferred work to take place.
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Users of the Z80 template may override this.
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*/
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void flush() {}
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int perform_machine_cycle(const MachineCycle *cycle) {
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return 0;
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}
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/*!
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Gets the flags register.
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@see set_flags
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@returns The current value of the flags register.
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*/
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uint8_t get_flags() {
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return
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carry_flag_ |
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(sign_result_ & Flag::Sign) |
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(bit5_result_ & Flag::Bit5) |
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half_carry_flag_ |
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(bit3_result_ & Flag::Bit3) |
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parity_overflow_flag_ |
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subtract_flag_;
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}
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/*!
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Sets the flags register.
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@see set_flags
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@param flags The new value of the flags register.
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*/
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void set_flags(uint8_t flags) {
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carry_flag_ = flags & Flag::Carry;
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sign_result_ = flags;
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bit5_result_ = flags;
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half_carry_flag_ = flags & Flag::HalfCarry;
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bit3_result_ = flags;
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parity_overflow_flag_ = flags & Flag::Parity;
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subtract_flag_ = flags & Flag::Subtract;
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}
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/*!
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Gets the value of a register.
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@see set_value_of_register
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@param r The register to set.
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@returns The value of the register. 8-bit registers will be returned as unsigned.
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*/
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uint16_t get_value_of_register(Register r) {
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switch (r) {
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case Register::ProgramCounter: return pc_.full;
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case Register::StackPointer: return sp_.full;
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case Register::A: return a_;
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case Register::Flags: return get_flags();
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case Register::AF: return (uint16_t)((a_ << 8) | get_flags());
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case Register::B: return bc_.bytes.high;
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case Register::C: return bc_.bytes.low;
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case Register::BC: return bc_.full;
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case Register::D: return de_.bytes.high;
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case Register::E: return de_.bytes.low;
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case Register::DE: return de_.full;
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case Register::H: return hl_.bytes.high;
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case Register::L: return hl_.bytes.low;
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case Register::HL: return hl_.full;
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case Register::ADash: return afDash_.bytes.high;
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case Register::FlagsDash: return afDash_.bytes.low;
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case Register::AFDash: return afDash_.full;
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case Register::BDash: return bcDash_.bytes.high;
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case Register::CDash: return bcDash_.bytes.low;
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case Register::BCDash: return bcDash_.full;
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case Register::DDash: return deDash_.bytes.high;
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case Register::EDash: return deDash_.bytes.low;
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case Register::DEDash: return deDash_.full;
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case Register::HDash: return hlDash_.bytes.high;
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case Register::LDash: return hlDash_.bytes.low;
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case Register::HLDash: return hlDash_.full;
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case Register::IXh: return ix_.bytes.high;
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case Register::IXl: return ix_.bytes.low;
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case Register::IX: return ix_.full;
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case Register::IYh: return iy_.bytes.high;
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case Register::IYl: return iy_.bytes.low;
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case Register::IY: return iy_.full;
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case Register::R: return r_;
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case Register::I: return i_;
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default: return 0;
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}
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}
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/*!
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Sets the value of a register.
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@see get_value_of_register
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@param r The register to set.
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@param value The value to set. If the register is only 8 bit, the value will be truncated.
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*/
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void set_value_of_register(Register r, uint16_t value) {
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switch (r) {
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case Register::ProgramCounter: pc_.full = value; break;
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case Register::StackPointer: sp_.full = value; break;
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case Register::A: a_ = (uint8_t)value; break;
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case Register::AF: a_ = (uint8_t)(value >> 8); // deliberate fallthrough...
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case Register::Flags: set_flags((uint8_t)value); break;
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case Register::B: bc_.bytes.high = (uint8_t)value; break;
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case Register::C: bc_.bytes.low = (uint8_t)value; break;
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case Register::BC: bc_.full = value; break;
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case Register::D: de_.bytes.high = (uint8_t)value; break;
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case Register::E: de_.bytes.low = (uint8_t)value; break;
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case Register::DE: de_.full = value; break;
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case Register::H: hl_.bytes.high = (uint8_t)value; break;
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case Register::L: hl_.bytes.low = (uint8_t)value; break;
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case Register::HL: hl_.full = value; break;
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case Register::ADash: afDash_.bytes.high = (uint8_t)value; break;
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case Register::FlagsDash: afDash_.bytes.low = (uint8_t)value; break;
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case Register::AFDash: afDash_.full = value; break;
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case Register::BDash: bcDash_.bytes.high = (uint8_t)value; break;
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case Register::CDash: bcDash_.bytes.low = (uint8_t)value; break;
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case Register::BCDash: bcDash_.full = value; break;
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case Register::DDash: deDash_.bytes.high = (uint8_t)value; break;
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case Register::EDash: deDash_.bytes.low = (uint8_t)value; break;
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case Register::DEDash: deDash_.full = value; break;
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case Register::HDash: hlDash_.bytes.high = (uint8_t)value; break;
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case Register::LDash: hlDash_.bytes.low = (uint8_t)value; break;
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case Register::HLDash: hlDash_.full = value; break;
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case Register::IXh: ix_.bytes.high = (uint8_t)value; break;
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case Register::IXl: ix_.bytes.low = (uint8_t)value; break;
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case Register::IX: ix_.full = value; break;
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case Register::IYh: iy_.bytes.high = (uint8_t)value; break;
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case Register::IYl: iy_.bytes.low = (uint8_t)value; break;
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case Register::IY: iy_.full = value; break;
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|
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case Register::R: r_ = (uint8_t)value; break;
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case Register::I: i_ = (uint8_t)value; break;
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default: break;
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}
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|
}
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};
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|
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}
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}
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#endif /* Z80_hpp */
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