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148 lines
3.8 KiB
C++
148 lines
3.8 KiB
C++
//
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// Copper.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/09/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef NDEBUG
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#define NDEBUG
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#endif
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#define LOG_PREFIX "[Copper] "
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#include "../../Outputs/Log.hpp"
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#include "Chipset.hpp"
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#include "Copper.hpp"
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using namespace Amiga;
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namespace {
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bool satisfies_raster(uint16_t position, uint16_t blitter_status, uint16_t *instruction) {
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const uint16_t mask = 0x8000 | (instruction[1] & 0x7ffe);
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return
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(position & mask) >= (instruction[0] & mask)
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&& (!(blitter_status & 0x4000) || (instruction[1] & 0x8000));
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}
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}
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//
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// Quick notes on the Copper:
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//
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// There are three instructions: move, wait and skip. All are two words in length.
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//
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// Move writes a value to one of the Chipset registers; it is encoded as:
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//
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// First word:
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// b0: 0
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// b1–b8: register address
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// b9+: unused ("should be set to 0")
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//
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// Second word:
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// b0–b15: value to move.
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//
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//
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// Wait waits until the raster gets to at least a certain position, and
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// optionally until the Blitter has finished. It is encoded as:
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//
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// First word:
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// b0: 1
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// b1–b7: horizontal beam position
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// b8+: vertical beam position
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//
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// Second word:
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// b0: 0
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// b1–b7: horizontal beam comparison mask
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// b8–b14: vertical beam comparison mask
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// b15: 1 => don't also wait for the Blitter to be finished; 0 => wait.
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//
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//
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// Skip skips the next instruction if the raster has already reached a certain
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// position, and optionally only if the Blitter has finished, and only if the
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// next instruction is a move.
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//
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// First word:
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// b0: 1
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// b1–b7: horizontal beam position
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// b8+: vertical beam position
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//
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// Second word:
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// b0: 1
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// b1–b7: horizontal beam comparison mask
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// b8–b14: vertical beam comparison mask
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// b15: 1 => don't also test whether the Blitter is finished; 0 => test.
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//
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bool Copper::advance_dma(uint16_t position, uint16_t blitter_status) {
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switch(state_) {
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default: return false;
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case State::Waiting:
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if(satisfies_raster(position, blitter_status, instruction_)) {
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LOG("Unblocked waiting for " << PADHEX(4) << instruction_[0] << " at " << position);
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state_ = State::FetchFirstWord;
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}
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return false;
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case State::FetchFirstWord:
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instruction_[0] = ram_[address_ & ram_mask_];
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++address_;
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state_ = State::FetchSecondWord;
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break;
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case State::FetchSecondWord: {
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// Get and reset the should-skip-next flag.
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const bool should_skip_move = skip_next_;
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skip_next_ = false;
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// Read in the second instruction word.
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instruction_[1] = ram_[address_ & ram_mask_];
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++address_;
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// Check for a MOVE.
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if(!(instruction_[0] & 1)) {
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if(!should_skip_move) {
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// Stop if this move would be a privilege violation.
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instruction_[0] &= 0x1fe;
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if((instruction_[0] < 0x10) || (instruction_[0] < 0x20 && !(control_&1))) {
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LOG("Invalid MOVE to " << PADHEX(4) << instruction_[0] << "; stopping");
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state_ = State::Stopped;
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break;
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}
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// Construct a 68000-esque Microcycle in order to be able to perform the access.
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CPU::MC68000::Microcycle cycle;
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cycle.operation = CPU::MC68000::Microcycle::SelectWord;
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uint32_t full_address = instruction_[0];
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CPU::RegisterPair16 data = instruction_[1];
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cycle.address = &full_address;
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cycle.value = &data;
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chipset_.perform(cycle);
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}
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// Roll onto the next command.
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state_ = State::FetchFirstWord;
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break;
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}
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// Got to here => this is a WAIT or a SKIP.
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if(!(instruction_[1] & 1)) {
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// A WAIT. Just note that this is now waiting; the proper test
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// will be applied from the next potential `advance_dma` onwards.
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state_ = State::Waiting;
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break;
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}
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// Neither a WAIT nor a MOVE => a SKIP.
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skip_next_ = satisfies_raster(position, blitter_status, instruction_);
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state_ = State::FetchFirstWord;
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} break;
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}
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return true;
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}
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