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330 lines
10 KiB
C++
330 lines
10 KiB
C++
//
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// 68000.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 08/03/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#ifndef MC68000_h
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#define MC68000_h
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#include <cstdint>
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#include <cstring>
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#include <iomanip>
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#include <iostream>
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#include <limits>
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#include <ostream>
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#include <vector>
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#include "../../ClockReceiver/ForceInline.hpp"
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#include "../../ClockReceiver/ClockReceiver.hpp"
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#include "../RegisterSizes.hpp"
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namespace CPU {
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namespace MC68000 {
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/*!
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A microcycle is an atomic unit of 68000 bus activity — it is a single item large enough
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fully to specify a sequence of bus events that occur without any possible interruption.
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Concretely, a standard read cycle breaks down into at least two microcycles:
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1) a 4 half-cycle length microcycle in which the address strobe is signalled; and
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2) a 4 half-cycle length microcycle in which at least one of the data strobes is
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signalled, and the data bus is sampled.
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That is, assuming DTack were signalled when microcycle (1) ended. If not then additional
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wait state microcycles would fall between those two parts.
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The 68000 data sheet defines when the address becomes valid during microcycle (1), and
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when the address strobe is actually asserted. But those timings are fixed. So simply
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telling you that this was a microcycle during which the address trobe was signalled is
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sufficient fully to describe the bus activity.
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(Aside: see the 68000 template's definition for options re: implicit DTack; if your
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68000 owner can always predict exactly how long it will hold DTack following observation
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of an address-strobing microcycle, it can just supply those periods for accounting and
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avoid the runtime cost of actual DTack emulation. But such as the bus allows.)
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*/
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struct Microcycle {
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/// A NewAddress cycle is one in which the address strobe is initially low but becomes high;
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/// this correlates to states 0 to 5 of a standard read/write cycle.
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static const int NewAddress = 1 << 0;
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/// A SameAddress cycle is one in which the address strobe is continuously asserted, but neither
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/// of the data strobes are.
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static const int SameAddress = 1 << 1;
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/// A Reset cycle is one in which the RESET output is asserted.
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static const int Reset = 1 << 2;
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/// Indicates that the address and both data select strobes are active.
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static const int SelectWord = 1 << 3;
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/// Indicates that the address strobe and exactly one of the data strobes are active; you can determine
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/// which by inspecting the low bit of the provided address. The RW line indicates a read.
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static const int SelectByte = 1 << 4;
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/// If set, indicates a read. Otherwise, a write.
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static const int Read = 1 << 5;
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/// Contains the value of line FC0 if it is not implicit via InterruptAcknowledge.
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static const int IsData = 1 << 6;
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/// Contains the value of line FC1 if it is not implicit via InterruptAcknowledge.
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static const int IsProgram = 1 << 7;
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/// The interrupt acknowledge cycle is that during which the 68000 seeks to obtain the vector for
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/// an interrupt it plans to observe. Noted on a real 68000 by all FCs being set to 1.
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static const int InterruptAcknowledge = 1 << 8;
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/// Represents the state of the 68000's valid memory address line — indicating whether this microcycle
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/// is synchronised with the E clock to satisfy a valid peripheral address request.
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static const int IsPeripheral = 1 << 9;
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/// Contains a valid combination of the various static const int flags, describing the operation
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/// performed by this Microcycle.
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int operation = 0;
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/// Describes the duration of this Microcycle.
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HalfCycles length = HalfCycles(4);
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/*!
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For expediency, this provides a full 32-bit byte-resolution address — e.g.
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if reading indirectly via an address register, this will indicate the full
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value of the address register.
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The receiver should ignore bits 0 and 24+. Use word_address() automatically
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to obtain the only the 68000's real address lines, giving a 23-bit address
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at word resolution.
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*/
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const uint32_t *address = nullptr;
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/*!
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If this is a write cycle, dereference value to get the value loaded onto
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the data bus.
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If this is a read cycle, write the value on the data bus to it.
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Otherwise, this value is undefined.
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Byte values are provided via @c value.halves.low. @c value.halves.high is undefined.
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This is true regardless of whether the upper or lower byte of a word is being
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accessed.
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Word values occupy the entirety of @c value.full.
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*/
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RegisterPair16 *value = nullptr;
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/// @returns @c true if two Microcycles are equal; @c false otherwise.
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bool operator ==(const Microcycle &rhs) const {
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if(value != rhs.value) return false;
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if(address != rhs.address) return false;
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if(length != rhs.length) return false;
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if(operation != rhs.operation) return false;
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return true;
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}
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// Various inspectors.
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/*! @returns true if any data select line is active; @c false otherwise. */
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forceinline bool data_select_active() const {
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return bool(operation & (SelectWord | SelectByte | InterruptAcknowledge));
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}
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/*!
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@returns 0 if this byte access wants the low part of a 16-bit word; 8 if it wants the high part.
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*/
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forceinline unsigned int byte_shift() const {
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return (((*address) & 1) << 3) ^ 8;
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}
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/*!
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Obtains the mask to apply to a word that will leave only the byte this microcycle is selecting.
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@returns 0x00ff if this byte access wants the low part of a 16-bit word; 0xff00 if it wants the high part.
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*/
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forceinline uint16_t byte_mask() const {
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return uint16_t(0xff00) >> (((*address) & 1) << 3);
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}
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/*!
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Obtains the mask to apply to a word that will leave only the byte this microcycle **isn't** selecting.
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i.e. this is the part of a word that should be untouched by this microcycle.
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@returns 0xff00 if this byte access wants the low part of a 16-bit word; 0x00ff if it wants the high part.
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*/
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forceinline uint16_t untouched_byte_mask() const {
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return uint16_t(uint16_t(0xff) << (((*address) & 1) << 3));
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}
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/*!
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Assuming this cycle is a byte write, mutates @c destination by writing the byte to the proper upper or
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lower part, retaining the other half.
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*/
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forceinline uint16_t write_byte(uint16_t destination) const {
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return uint16_t((destination & untouched_byte_mask()) | (value->halves.low << byte_shift()));
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}
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/*!
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@returns non-zero if this is a byte read and 68000 LDS is asserted.
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*/
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forceinline int lower_data_select() const {
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return (operation & SelectByte) & ((*address & 1) << 3);
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}
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/*!
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@returns non-zero if this is a byte read and 68000 UDS is asserted.
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*/
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forceinline int upper_data_select() const {
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return (operation & SelectByte) & ~((*address & 1) << 3);
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}
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/*!
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@returns the address being accessed at the precision a 68000 supplies it —
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only 24 address bit precision, with the low bit shifted out. So it's the
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68000 address at word precision: address 0 is the first word in the address
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space, address 1 is the second word (i.e. the third and fourth bytes) in
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the address space, etc.
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*/
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forceinline uint32_t word_address() const {
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return (address ? (*address) & 0x00fffffe : 0) >> 1;
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}
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/*!
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@returns the same value as word_address() for any Microcycle with the NewAddress or
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SameAddress flags set; undefined behaviour otherwise.
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*/
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forceinline uint32_t active_operation_word_address() const {
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return ((*address) & 0x00fffffe) >> 1;
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}
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#ifndef NDEBUG
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bool is_resizeable = false;
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#endif
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};
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/*!
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This is the prototype for a 68000 bus handler; real bus handlers can descend from this
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in order to get default implementations of any changes that may occur in the expected interface.
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*/
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class BusHandler {
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public:
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/*!
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Provides the bus handler with a single Microcycle to 'perform'.
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FC0 and FC1 are provided inside the microcycle as the IsData and IsProgram
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flags; FC2 is provided here as is_supervisor — it'll be either 0 or 1.
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*/
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HalfCycles perform_bus_operation(const Microcycle &cycle, int is_supervisor) {
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return HalfCycles(0);
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}
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void flush() {}
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/*!
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Provides information about the path of execution if enabled via the template.
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*/
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void will_perform(uint32_t address, uint16_t opcode) {}
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};
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#include "Implementation/68000Storage.hpp"
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class ProcessorBase: public ProcessorStorage {
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};
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enum Flag: uint16_t {
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Trace = 0x8000,
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Supervisor = 0x2000,
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ConditionCodes = 0x1f,
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Extend = 0x0010,
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Negative = 0x0008,
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Zero = 0x0004,
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Overflow = 0x0002,
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Carry = 0x0001
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};
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struct ProcessorState {
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uint32_t data[8];
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uint32_t address[7];
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uint32_t user_stack_pointer, supervisor_stack_pointer;
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uint32_t program_counter;
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uint16_t status;
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/*!
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@returns the supervisor stack pointer if @c status indicates that
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the processor is in supervisor mode; the user stack pointer otherwise.
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*/
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uint32_t stack_pointer() const {
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return (status & Flag::Supervisor) ? supervisor_stack_pointer : user_stack_pointer;
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}
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// TODO: More state needed to indicate current instruction, the processor's
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// progress through it, and anything it has fetched so far.
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// uint16_t current_instruction;
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};
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template <class T, bool dtack_is_implicit, bool signal_will_perform = false> class Processor: public ProcessorBase {
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public:
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Processor(T &bus_handler) : ProcessorBase(), bus_handler_(bus_handler) {}
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void run_for(HalfCycles duration);
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using State = ProcessorState;
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/// @returns The current processor state.
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State get_state();
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/// Sets the processor to the supplied state.
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void set_state(const State &);
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/// Sets the DTack line — @c true for active, @c false for inactive.
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inline void set_dtack(bool dtack) {
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dtack_ = dtack;
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}
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/// Sets the VPA (valid peripheral address) line — @c true for active, @c false for inactive.
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inline void set_is_peripheral_address(bool is_peripheral_address) {
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is_peripheral_address_ = is_peripheral_address;
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}
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/// Sets the bus error line — @c true for active, @c false for inactive.
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inline void set_bus_error(bool bus_error) {
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bus_error_ = bus_error;
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}
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/// Sets the interrupt lines, IPL0, IPL1 and IPL2.
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inline void set_interrupt_level(int interrupt_level) {
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bus_interrupt_level_ = interrupt_level;
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}
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/// Sets the bus request line.
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/// This are of functionality is TODO.
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inline void set_bus_request(bool bus_request) {
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bus_request_ = bus_request;
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}
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/// Sets the bus acknowledge line.
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/// This are of functionality is TODO.
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inline void set_bus_acknowledge(bool bus_acknowledge) {
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bus_acknowledge_ = bus_acknowledge;
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}
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/// Sets the halt line.
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inline void set_halt(bool halt) {
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halt_ = halt;
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}
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private:
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T &bus_handler_;
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};
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#include "Implementation/68000Implementation.hpp"
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}
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}
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#endif /* MC68000_h */
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