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mirror of https://github.com/TomHarte/CLK.git synced 2024-06-30 22:29:56 +00:00
CLK/Processors
Thomas Harte f529eadbec Corrects 16-bit read-modify-write.
Subject to the TODO proviso on 'correct'; has my 6502 prejudice pushed me into unrealistic bus signalling?
2020-10-12 18:36:09 -04:00
..
6502 Starts using Jeek816 for a basic native-mode audit. Fixes absolute long addressing. 2020-10-11 22:02:46 -04:00
6502Esque Attempts proactively to ensure proper RTI behaviour on the 65816. 2020-10-11 15:25:13 -04:00
65816 Corrects 16-bit read-modify-write. 2020-10-12 18:36:09 -04:00
68000 Increases likelihood of 68000 Program offset-size assumptions being met. 2020-07-02 22:24:04 -04:00
Z80 Resolve various test-case warnings. 2020-09-27 15:10:29 -04:00
AllRAMProcessor.cpp Ups the 65816 test machine to a full 16mb RAM. 2020-10-11 21:18:01 -04:00
AllRAMProcessor.hpp Ups the 65816 test machine to a full 16mb RAM. 2020-10-11 21:18:01 -04:00
RegisterSizes.hpp Embraces a more communicative 68000 bus. 2019-03-10 17:27:34 -04:00