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331 lines
10 KiB
Plaintext
331 lines
10 KiB
Plaintext
//
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// 65816ComparativeTests.m
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// Clock SignalTests
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//
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// Created by Thomas Harte on 18/06/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#include "65816.hpp"
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#import <XCTest/XCTest.h>
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#include <array>
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#include <optional>
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#include <vector>
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#include <unordered_map>
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#include "6502Selector.hpp"
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namespace {
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struct StopException {};
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template <CPU::MOS6502Esque::Type type>
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struct BusHandler: public CPU::MOS6502Esque::BusHandlerT<type> {
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using AddressType = typename CPU::MOS6502Esque::BusHandlerT<type>::AddressType;
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// Use a map to store RAM contents, in order to preserve initialised state.
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std::unordered_map<AddressType, uint8_t> ram;
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std::unordered_map<AddressType, uint8_t> inventions;
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Cycles perform_bus_operation(CPU::MOS6502Esque::BusOperation operation, AddressType address, uint8_t *value) {
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// Record the basics of the operation.
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auto &cycle = cycles.emplace_back();
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cycle.operation = operation;
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if constexpr (has_extended_bus_output(type)) {
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cycle.extended_bus = processor.get_extended_bus_output();
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}
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// Perform the operation, and fill in the cycle's value.
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using BusOperation = CPU::MOS6502Esque::BusOperation;
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auto ram_value = ram.find(address);
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switch(operation) {
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case BusOperation::ReadOpcode:
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if(initial_pc && (*initial_pc != address || !allow_pc_repetition)) {
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cycles.pop_back();
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pc_overshoot = -1;
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throw StopException();
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}
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initial_pc = address;
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[[fallthrough]];
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case BusOperation::Read:
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case BusOperation::ReadProgram:
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case BusOperation::ReadVector:
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cycle.address = address;
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if(ram_value != ram.end()) {
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cycle.value = *value = ram_value->second;
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} else {
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cycle.value = *value = uint8_t(rand() >> 8);
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inventions[address] = ram[address] = *cycle.value;
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}
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break;
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case BusOperation::Write:
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cycle.address = address;
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cycle.value = ram[address] = *value;
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break;
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case BusOperation::Ready:
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case BusOperation::None:
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throw StopException();
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break;
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case BusOperation::InternalOperationWrite:
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cycle.value = *value = ram_value->second;
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[[fallthrough]];
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case BusOperation::InternalOperationRead:
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cycle.address = address;
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break;
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default: assert(false);
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}
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// Don't occupy any bonus time.
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return Cycles(1);
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}
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void setup(uint8_t opcode) {
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ram.clear();
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inventions.clear();
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cycles.clear();
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pc_overshoot = 0;
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initial_pc = std::nullopt;
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// For MVP or MVN, keep tracking fetches via the same location.
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// For other instructions, don't. That's to avoid endless loops
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// for flow control that happens to jump back to where it began.
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allow_pc_repetition = opcode == 0x54 || opcode == 0x44;
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using Register = CPU::MOS6502Esque::Register;
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const auto pc =
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AddressType(
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processor.value_of(Register::ProgramCounter) |
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(processor.value_of(Register::ProgramBank) << 16)
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);
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inventions[pc] = ram[pc] = opcode;
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}
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int pc_overshoot = 0;
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std::optional<AddressType> initial_pc;
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bool allow_pc_repetition = false;
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struct Cycle {
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CPU::MOS6502Esque::BusOperation operation;
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std::optional<AddressType> address;
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std::optional<uint8_t> value;
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int extended_bus = 0;
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};
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std::vector<Cycle> cycles;
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CPU::MOS6502Esque::Processor<type, BusHandler<type>, false> processor;
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BusHandler() : processor(*this) {
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// Never run the official reset procedure.
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processor.set_power_on(false);
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}
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};
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template <bool has_emulation, typename Processor> void print_registers(FILE *file, const Processor &processor, int pc_offset) {
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using Register = CPU::MOS6502Esque::Register;
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fprintf(file, "\"pc\": %d, ", (processor.value_of(Register::ProgramCounter) + pc_offset) & 65535);
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fprintf(file, "\"s\": %d, ", processor.value_of(Register::StackPointer));
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fprintf(file, "\"a\": %d, ", processor.value_of(Register::A));
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fprintf(file, "\"x\": %d, ", processor.value_of(Register::X));
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fprintf(file, "\"y\": %d, ", processor.value_of(Register::Y));
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fprintf(file, "\"p\": %d, ", processor.value_of(Register::Flags));
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if constexpr (has_emulation) {
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fprintf(file, "\"dbr\": %d, ", processor.value_of(Register::DataBank));
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fprintf(file, "\"d\": %d, ", processor.value_of(Register::Direct));
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fprintf(file, "\"pbr\": %d, ", processor.value_of(Register::ProgramBank));
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fprintf(file, "\"e\": %d, ", processor.value_of(Register::EmulationFlag));
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}
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}
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template <typename IntT>
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void print_ram(FILE *file, const std::unordered_map<IntT, uint8_t> &data) {
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fprintf(file, "\"ram\": [");
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bool is_first = true;
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for(const auto &pair: data) {
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if(!is_first) fprintf(file, ", ");
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is_first = false;
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fprintf(file, "[%d, %d]", pair.first, pair.second);
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}
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fprintf(file, "]");
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}
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// MARK: - New test generator.
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template <CPU::MOS6502Esque::Type type> void generate() {
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BusHandler<type> handler;
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constexpr bool has_emulation = has(type, CPU::MOS6502Esque::Register::EmulationFlag);
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NSString *const tempDir = NSTemporaryDirectory();
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NSLog(@"Outputting to %@", tempDir);
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for(int operation = 0; operation < (has_emulation ? 512 : 256); operation++) {
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// Make tests repeatable, at least for any given instance of
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// the runtime.
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constexpr auto type_offset = int(CPU::MOS6502Esque::Type::TWDC65816) - int(type);
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srand(65816 + operation + type_offset);
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const bool is_emulated = operation & 256;
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const uint8_t opcode = operation & 255;
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NSString *const targetName =
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has_emulation ?
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[NSString stringWithFormat:@"%@%02x.%c.json", tempDir, opcode, is_emulated ? 'e' : 'n'] :
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[NSString stringWithFormat:@"%@%02x.json", tempDir, opcode];
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FILE *const target = fopen(targetName.UTF8String, "wt");
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bool is_first_test = true;
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fprintf(target, "[");
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for(int test = 0; test < 10'000; test++) {
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if(!is_first_test) fprintf(target, ",\n");
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is_first_test = false;
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// Ensure processor's next action is an opcode fetch.
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handler.processor.restart_operation_fetch();
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// Randomise most of the processor state...
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using Register = CPU::MOS6502Esque::Register;
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handler.processor.set_value_of(Register::A, rand() >> 8);
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handler.processor.set_value_of(Register::Flags, rand() >> 8);
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handler.processor.set_value_of(Register::X, rand() >> 8);
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handler.processor.set_value_of(Register::Y, rand() >> 8);
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handler.processor.set_value_of(Register::ProgramCounter, rand() >> 8);
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handler.processor.set_value_of(Register::StackPointer, rand() >> 8);
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if(has_emulation) {
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handler.processor.set_value_of(Register::DataBank, rand() >> 8);
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handler.processor.set_value_of(Register::ProgramBank, rand() >> 8);
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handler.processor.set_value_of(Register::Direct, rand() >> 8);
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// ... except for emulation mode, which is a given.
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// And is set last to ensure proper internal state is applied.
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handler.processor.set_value_of(Register::EmulationFlag, is_emulated);
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}
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// Establish the opcode.
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handler.setup(opcode);
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// Dump initial state.
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if(has_emulation) {
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fprintf(target, "{ \"name\": \"%02x %c %d\", ", opcode, is_emulated ? 'e' : 'n', test + 1);
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} else {
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fprintf(target, "{ \"name\": \"%02x %d\", ", opcode, test + 1);
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}
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fprintf(target, "\"initial\": {");
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print_registers<has_emulation>(target, handler.processor, 0);
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// Run to the second opcode fetch.
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try {
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handler.processor.run_for(Cycles(100));
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} catch (const StopException &) {}
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// Dump all inventions as initial memory state.
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print_ram(target, handler.inventions);
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// Dump final state.
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fprintf(target, "}, \"final\": {");
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print_registers<has_emulation>(target, handler.processor, handler.pc_overshoot);
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print_ram(target, handler.ram);
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fprintf(target, "}, ");
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// Append cycles.
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fprintf(target, "\"cycles\": [");
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bool is_first_cycle = true;
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for(const auto &cycle: handler.cycles) {
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if(!is_first_cycle) fprintf(target, ",");
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is_first_cycle = false;
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bool vda = false;
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bool vpa = false;
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bool vpb = false;
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bool read = false;
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bool wait = false;
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using BusOperation = CPU::MOS6502Esque::BusOperation;
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switch(cycle.operation) {
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case BusOperation::Read: read = vda = true; break;
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case BusOperation::ReadOpcode: read = vda = vpa = true; break;
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case BusOperation::ReadProgram: read = vpa = true; break;
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case BusOperation::ReadVector: read = vpb = vda = true; break;
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case BusOperation::InternalOperationRead: read = true; break;
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case BusOperation::Write: vda = true; break;
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case BusOperation::InternalOperationWrite: break;
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case BusOperation::None:
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case BusOperation::Ready: wait = true; break;
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default:
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assert(false);
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}
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fprintf(target, "[");
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if(cycle.address) {
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fprintf(target, "%d, ", *cycle.address);
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} else {
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fprintf(target, "null, ");
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}
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if(cycle.value) {
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fprintf(target, "%d, ", *cycle.value);
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} else {
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fprintf(target, "null, ");
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}
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if(has_emulation) {
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using ExtendedBusOutput = CPU::WDC65816::ExtendedBusOutput;
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const bool emulation = cycle.extended_bus & ExtendedBusOutput::Emulation;
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const bool memory_size = cycle.extended_bus & ExtendedBusOutput::MemorySize;
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const bool index_size = cycle.extended_bus & ExtendedBusOutput::IndexSize;
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const bool memory_lock = cycle.extended_bus & ExtendedBusOutput::MemoryLock;
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fprintf(target, "\"%c%c%c%c%c%c%c%c\"]",
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vda ? 'd' : '-',
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vpa ? 'p' : '-',
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vpb ? 'v' : '-',
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wait ? '-' : (read ? 'r' : 'w'),
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wait ? '-' : (emulation ? 'e' : '-'),
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wait ? '-' : (memory_size ? 'm' : '-'),
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wait ? '-' : (index_size ? 'x' : '-'),
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wait ? '-' : (memory_lock ? 'l' : '-')
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);
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} else {
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if(read) {
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fprintf(target, "\"read\"]");
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} else {
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fprintf(target, "\"write\"]");
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}
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}
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}
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// Terminate object.
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fprintf(target, "]}");
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}
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fprintf(target, "]");
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fclose(target);
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}
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}
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}
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// MARK: - Existing test evaluator.
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@interface WDC65816ComparativeTests : XCTestCase
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@end
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@implementation WDC65816ComparativeTests
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// A generator for tests; not intended to be a permanent fixture.
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//- (void)testGenerate {
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// generate<CPU::MOS6502Esque::Type::TWDC65816>();
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//}
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@end
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