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CLK
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CLK
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Thomas Harte
fa19e2d9c2
Removes some detritus.
2017-08-24 22:00:21 -04:00
..
6502
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Z80
Removes some detritus.
2017-08-24 22:00:21 -04:00
AllRAMProcessor.cpp
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
AllRAMProcessor.hpp
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
RegisterSizes.hpp
Noodled around with initial state.
2017-05-29 19:25:08 -04:00