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116 lines
3.3 KiB
Plaintext
116 lines
3.3 KiB
Plaintext
//
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// EmuTOSTests.m
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// Clock SignalTests
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//
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// Created by Thomas Harte on 10/03/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#import <XCTest/XCTest.h>
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#include <array>
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#include <cassert>
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#include <iostream>
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#include <fstream>
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#include <zlib.h>
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#include "68000.hpp"
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#include "Comparative68000.hpp"
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#include "CSROMFetcher.hpp"
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class QL: public ComparativeBusHandler {
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public:
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QL(const std::vector<uint8_t> &rom, const char *trace_name) : ComparativeBusHandler(trace_name), m68000_(*this) {
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assert(!(rom.size() & 1));
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rom_.resize(rom.size() / 2);
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for(size_t c = 0; c < rom_.size(); ++c) {
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rom_[c] = (rom[c << 1] << 8) | rom[(c << 1) + 1];
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}
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}
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void run_for(HalfCycles cycles) {
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m68000_.run_for(cycles);
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}
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CPU::MC68000::State get_state() final {
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return m68000_.get_state();
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}
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using Microcycle = CPU::MC68000::Microcycle;
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template <Microcycle::OperationT op> HalfCycles perform_bus_operation(const Microcycle &cycle, int) {
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const uint32_t address = cycle.word_address();
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uint32_t word_address = address;
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// QL memory map: ROM is in the lowest area; RAM is from 0x20000.
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const bool is_rom = word_address < rom_.size();
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const bool is_ram = word_address >= 0x10000 && word_address < 0x10000+ram_.size();
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const bool is_peripheral = !is_ram && !is_rom;
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uint16_t *const base = is_rom ? rom_.data() : ram_.data();
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if(is_rom) {
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word_address %= rom_.size();
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}
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if(is_ram) {
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word_address %= ram_.size();
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}
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if(cycle.data_select_active()) {
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uint16_t peripheral_result = 0xffff;
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const auto operation = (op != Microcycle::DecodeDynamically) ? op : cycle.operation;
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switch(operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
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default: break;
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->w = is_peripheral ? peripheral_result : base[word_address];
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->b = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
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break;
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case Microcycle::SelectWord:
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assert(!(is_rom && !is_peripheral));
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if(!is_peripheral) base[word_address] = cycle.value->w;
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break;
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case Microcycle::SelectByte:
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assert(!(is_rom && !is_peripheral));
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if(!is_peripheral) base[word_address] = (cycle.value->b << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
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break;
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}
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}
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return HalfCycles(0);
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}
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private:
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CPU::MC68000::Processor<QL, true, false, true> m68000_;
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std::vector<uint16_t> rom_;
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std::array<uint16_t, 64*1024> ram_;
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};
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@interface QLTests : XCTestCase
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@end
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@implementation QLTests {
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std::unique_ptr<QL> _machine;
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}
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/*!
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Tests the progression of Clock Signal's 68000 through the Sinclair QL's ROM against a known-good trace.
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*/
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- (void)testStartup {
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constexpr ROM::Name rom_name = ROM::Name::SinclairQLJS;
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ROM::Request request(rom_name);
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const auto roms = CSROMFetcher()(request);
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NSString *const traceLocation = [[NSBundle bundleForClass:[self class]] pathForResource:@"qltrace" ofType:@".txt.gz"];
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_machine = std::make_unique<QL>(roms.find(rom_name)->second, traceLocation.UTF8String);
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// This is how many cycles it takes to exhaust the supplied trace file.
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_machine->run_for(HalfCycles(23923180));
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}
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@end
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