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864 lines
28 KiB
C++
864 lines
28 KiB
C++
//
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// 9918Base.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 14/12/2017.
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// Copyright 2017 Thomas Harte. All rights reserved.
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//
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#ifndef TMS9918Base_hpp
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#define TMS9918Base_hpp
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#include "../../../Outputs/CRT/CRT.hpp"
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#include "../../../ClockReceiver/ClockReceiver.hpp"
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#include <cassert>
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#include <cstdint>
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#include <memory>
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#include <vector>
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namespace TI {
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namespace TMS {
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enum Personality {
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TMS9918A, // includes the 9928 and 9929; set TV standard and output device as desired.
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V9938,
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V9958,
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SMSVDP,
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SMS2VDP,
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GGVDP,
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};
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enum class TVStandard {
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/*! i.e. 50Hz output at around 312.5 lines/field */
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PAL,
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/*! i.e. 60Hz output at around 262.5 lines/field */
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NTSC
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};
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#define is_sega_vdp(x) ((x) >= SMSVDP)
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class Base {
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public:
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static uint32_t palette_pack(uint8_t r, uint8_t g, uint8_t b) {
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uint32_t result = 0;
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uint8_t *const result_ptr = reinterpret_cast<uint8_t *>(&result);
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result_ptr[0] = r;
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result_ptr[1] = g;
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result_ptr[2] = b;
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result_ptr[3] = 0;
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return result;
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}
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protected:
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static constexpr int output_lag = 11; // i.e. pixel output will occur 11 cycles after corresponding data read.
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// The default TMS palette.
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const uint32_t palette[16] = {
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palette_pack(0, 0, 0),
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palette_pack(0, 0, 0),
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palette_pack(33, 200, 66),
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palette_pack(94, 220, 120),
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palette_pack(84, 85, 237),
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palette_pack(125, 118, 252),
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palette_pack(212, 82, 77),
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palette_pack(66, 235, 245),
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palette_pack(252, 85, 84),
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palette_pack(255, 121, 120),
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palette_pack(212, 193, 84),
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palette_pack(230, 206, 128),
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palette_pack(33, 176, 59),
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palette_pack(201, 91, 186),
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palette_pack(204, 204, 204),
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palette_pack(255, 255, 255)
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};
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Base(Personality p);
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const Personality personality_;
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Outputs::CRT::CRT crt_;
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TVStandard tv_standard_ = TVStandard::NTSC;
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// Holds the contents of this VDP's connected DRAM.
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std::vector<uint8_t> ram_;
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// Holds the state of the DRAM/CRAM-access mechanism.
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uint16_t ram_pointer_ = 0;
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uint8_t read_ahead_buffer_ = 0;
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enum class MemoryAccess {
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Read, Write, None
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} queued_access_ = MemoryAccess::None;
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int cycles_until_access_ = 0;
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int minimum_access_column_ = 0;
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int vram_access_delay() {
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// This seems to be correct for all currently-modelled VDPs;
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// it's the delay between an external device scheduling a
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// read or write and the very first time that can occur
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// (though, in practice, it won't happen until the next
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// external slot after this number of cycles after the
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// device has requested the read or write).
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return 6;
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}
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// Holds the main status register.
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uint8_t status_ = 0;
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// Current state of programmer input.
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bool write_phase_ = false; // Determines whether the VDP is expecting the low or high byte of a write.
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uint8_t low_write_ = 0; // Buffers the low byte of a write.
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// Various programmable flags.
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bool mode1_enable_ = false;
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bool mode2_enable_ = false;
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bool mode3_enable_ = false;
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bool blank_display_ = false;
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bool sprites_16x16_ = false;
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bool sprites_magnified_ = false;
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bool generate_interrupts_ = false;
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int sprite_height_ = 8;
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size_t pattern_name_address_ = 0; // i.e. address of the tile map.
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size_t colour_table_address_ = 0; // address of the colour map (if applicable).
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size_t pattern_generator_table_address_ = 0; // address of the tile contents.
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size_t sprite_attribute_table_address_ = 0; // address of the sprite list.
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size_t sprite_generator_table_address_ = 0; // address of the sprite contents.
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uint8_t text_colour_ = 0;
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uint8_t background_colour_ = 0;
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// This implementation of this chip officially accepts a 3.58Mhz clock, but runs
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// internally at 5.37Mhz. The following two help to maintain a lossless conversion
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// from the one to the other.
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int cycles_error_ = 0;
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HalfCycles half_cycles_before_internal_cycles(int internal_cycles);
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// Internal mechanisms for position tracking.
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int latched_column_ = 0;
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// A helper function to output the current border colour for
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// the number of cycles supplied.
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void output_border(int cycles, uint32_t cram_dot);
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// A struct to contain timing information for the current mode.
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struct {
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/*
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Vertical layout:
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Lines 0 to [pixel_lines]: standard data fetch and drawing will occur.
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... to [first_vsync_line]: refresh fetches will occur and border will be output.
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.. to [2.5 or 3 lines later]: vertical sync is output.
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... to [total lines - 1]: refresh fetches will occur and border will be output.
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... for one line: standard data fetch will occur, without drawing.
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*/
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int total_lines = 262;
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int pixel_lines = 192;
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int first_vsync_line = 227;
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// Maximum number of sprite slots to populate;
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// if sprites beyond this number should be visible
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// then the appropriate status information will be set.
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int maximum_visible_sprites = 4;
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// Set the position, in cycles, of the two interrupts,
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// within a line.
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struct {
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int column = 4;
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int row = 193;
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} end_of_frame_interrupt_position;
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int line_interrupt_position = -1;
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// Enables or disabled the recognition of the sprite
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// list terminator, and sets the terminator value.
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bool allow_sprite_terminator = true;
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uint8_t sprite_terminator = 0xd0;
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} mode_timing_;
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uint8_t line_interrupt_target = 0xff;
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uint8_t line_interrupt_counter = 0;
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bool enable_line_interrupts_ = false;
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bool line_interrupt_pending_ = false;
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// The screen mode is a necessary predecessor to picking the line mode,
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// which is the thing latched per line.
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enum class ScreenMode {
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Blank,
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Text,
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MultiColour,
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ColouredText,
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Graphics,
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SMSMode4
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} screen_mode_;
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enum class LineMode {
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Text,
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Character,
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Refresh,
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SMS
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};
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// Temporary buffers collect a representation of this line prior to pixel serialisation.
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struct LineBuffer {
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// The line mode describes the proper timing diagram for this line.
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LineMode line_mode = LineMode::Text;
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// Holds the horizontal scroll position to apply to this line;
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// of those VDPs currently implemented, affects the Master System only.
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uint8_t latched_horizontal_scroll = 0;
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// The names array holds pattern names, as an offset into memory, and
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// potentially flags also.
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struct {
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size_t offset = 0;
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uint8_t flags = 0;
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} names[40];
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// The patterns array holds tile patterns, corresponding 1:1 with names.
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// Four bytes per pattern is the maximum required by any
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// currently-implemented VDP.
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uint8_t patterns[40][4];
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/*
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Horizontal layout (on a 342-cycle clock):
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15 cycles right border
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58 cycles blanking & sync
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13 cycles left border
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... i.e. to cycle 86, then:
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border up to first_pixel_output_column;
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pixels up to next_border_column;
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border up to the end.
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e.g. standard 256-pixel modes will want to set
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first_pixel_output_column = 86, next_border_column = 342.
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*/
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int first_pixel_output_column = 94;
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int next_border_column = 334;
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// An active sprite is one that has been selected for composition onto
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// this line.
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struct ActiveSprite {
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int index = 0; // The original in-table index of this sprite.
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int row = 0; // The row of the sprite that should be drawn.
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int x = 0; // The sprite's x position on screen.
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uint8_t image[4]; // Up to four bytes of image information.
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int shift_position = 0; // An offset representing how much of the image information has already been drawn.
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} active_sprites[8];
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int active_sprite_slot = 0; // A pointer to the slot into which a new active sprite will be deposited, if required.
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bool sprites_stopped = false; // A special TMS feature is that a sentinel value can be used to prevent any further sprites
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// being evaluated for display. This flag determines whether the sentinel has yet been reached.
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void reset_sprite_collection();
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} line_buffers_[313];
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void posit_sprite(LineBuffer &buffer, int sprite_number, int sprite_y, int screen_row);
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// There is a delay between reading into the line buffer and outputting from there to the screen. That delay
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// is observeable because reading time affects availability of memory accesses and therefore time in which
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// to update sprites and tiles, but writing time affects when the palette is used and when the collision flag
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// may end up being set. So the two processes are slightly decoupled. The end of reading one line may overlap
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// with the beginning of writing the next, hence the two separate line buffers.
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struct LineBufferPointer {
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int row, column;
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} read_pointer_, write_pointer_;
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// The SMS VDP has a programmer-set colour palette, with a dedicated patch of RAM. But the RAM is only exactly
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// fast enough for the pixel clock. So when the programmer writes to it, that causes a one-pixel glitch; there
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// isn't the bandwidth for the read both write to occur simultaneously. The following buffer therefore keeps
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// track of pending collisions, for visual reproduction.
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struct CRAMDot {
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LineBufferPointer location;
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uint32_t value;
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};
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std::vector<CRAMDot> upcoming_cram_dots_;
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// Extra information that affects the Master System output mode.
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struct {
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// Programmer-set flags.
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bool vertical_scroll_lock = false;
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bool horizontal_scroll_lock = false;
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bool hide_left_column = false;
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bool shift_sprites_8px_left = false;
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bool mode4_enable = false;
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uint8_t horizontal_scroll = 0;
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uint8_t vertical_scroll = 0;
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// The Master System's additional colour RAM.
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uint32_t colour_ram[32];
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bool cram_is_selected = false;
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// Holds the vertical scroll position for this frame; this is latched
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// once and cannot dynamically be changed until the next frame.
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uint8_t latched_vertical_scroll = 0;
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size_t pattern_name_address;
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size_t sprite_attribute_table_address;
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size_t sprite_generator_table_address;
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} master_system_;
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void set_current_screen_mode() {
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if(blank_display_) {
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screen_mode_ = ScreenMode::Blank;
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return;
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}
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if(is_sega_vdp(personality_) && master_system_.mode4_enable) {
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screen_mode_ = ScreenMode::SMSMode4;
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mode_timing_.maximum_visible_sprites = 8;
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return;
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}
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mode_timing_.maximum_visible_sprites = 4;
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if(!mode1_enable_ && !mode2_enable_ && !mode3_enable_) {
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screen_mode_ = ScreenMode::ColouredText;
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return;
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}
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if(mode1_enable_ && !mode2_enable_ && !mode3_enable_) {
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screen_mode_ = ScreenMode::Text;
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return;
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}
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if(!mode1_enable_ && mode2_enable_ && !mode3_enable_) {
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screen_mode_ = ScreenMode::Graphics;
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return;
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}
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if(!mode1_enable_ && !mode2_enable_ && mode3_enable_) {
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screen_mode_ = ScreenMode::MultiColour;
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return;
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}
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// TODO: undocumented TMS modes.
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screen_mode_ = ScreenMode::Blank;
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}
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void do_external_slot(int access_column) {
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// Don't do anything if the required time for the access to become executable
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// has yet to pass.
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if(access_column < minimum_access_column_) {
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return;
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}
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switch(queued_access_) {
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default: return;
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case MemoryAccess::Write:
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if(master_system_.cram_is_selected) {
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// Adjust the palette. In a Master System blue has a slightly different
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// scale; cf. https://www.retrorgb.com/sega-master-system-non-linear-blue-channel-findings.html
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constexpr uint8_t rg_scale[] = {0, 85, 170, 255};
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constexpr uint8_t b_scale[] = {0, 104, 170, 255};
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master_system_.colour_ram[ram_pointer_ & 0x1f] = palette_pack(
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rg_scale[(read_ahead_buffer_ >> 0) & 3],
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rg_scale[(read_ahead_buffer_ >> 2) & 3],
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b_scale[(read_ahead_buffer_ >> 4) & 3]
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);
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// Schedule a CRAM dot; this is scheduled for wherever it should appear
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// on screen. So it's wherever the output stream would be now. Which
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// is output_lag cycles ago from the point of view of the input stream.
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upcoming_cram_dots_.emplace_back();
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CRAMDot &dot = upcoming_cram_dots_.back();
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dot.location.column = write_pointer_.column - output_lag;
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dot.location.row = write_pointer_.row;
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// Handle before this row conditionally; then handle after (or, more realistically,
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// exactly at the end of) naturally.
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if(dot.location.column < 0) {
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--dot.location.row;
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dot.location.column += 342;
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}
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dot.location.row += dot.location.column / 342;
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dot.location.column %= 342;
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dot.value = master_system_.colour_ram[ram_pointer_ & 0x1f];
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} else {
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ram_[ram_pointer_ & 16383] = read_ahead_buffer_;
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}
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break;
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case MemoryAccess::Read:
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read_ahead_buffer_ = ram_[ram_pointer_ & 16383];
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break;
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}
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++ram_pointer_;
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queued_access_ = MemoryAccess::None;
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}
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/*
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Fetching routines follow below; they obey the following rules:
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1) input is a start position and an end position; they should perform the proper
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operations for the period: start <= time < end.
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2) times are measured relative to a 172-cycles-per-line clock (so: they directly
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count access windows on the TMS and Master System).
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3) time 0 is the beginning of the access window immediately after the last pattern/data
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block fetch that would contribute to this line, in a normal 32-column mode. So:
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* it's cycle 309 on Mattias' TMS diagram;
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* it's cycle 1238 on his V9938 diagram;
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* it's after the last background render block in Mask of Destiny's Master System timing diagram.
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That division point was selected, albeit arbitrarily, because it puts all the tile
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fetches for a single line into the same [0, 171] period.
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4) all of these functions are templated with a `use_end` parameter. That will be true if
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end is < 172, false otherwise. So functions can use it to eliminate should-exit-not checks,
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for the more usual path of execution.
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Provided for the benefit of the methods below:
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* the function external_slot(), which will perform any pending VRAM read/write.
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* the macros slot(n) and external_slot(n) which can be used to schedule those things inside a
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switch(start)-based implementation.
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All functions should just spool data to intermediary storage. This is because for most VDPs there is
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a decoupling between fetch pattern and output pattern, and it's neater to keep the same division
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for the exceptions.
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*/
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#define slot(n) \
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if(use_end && end == n) return; \
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[[fallthrough]]; \
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case n
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#define external_slot(n) \
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slot(n): do_external_slot((n)*2);
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#define external_slots_2(n) \
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external_slot(n); \
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external_slot(n+1);
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#define external_slots_4(n) \
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external_slots_2(n); \
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external_slots_2(n+2);
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#define external_slots_8(n) \
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external_slots_4(n); \
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external_slots_4(n+4);
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#define external_slots_16(n) \
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external_slots_8(n); \
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external_slots_8(n+8);
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#define external_slots_32(n) \
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external_slots_16(n); \
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external_slots_16(n+16);
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/***********************************************
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TMS9918 Fetching Code
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************************************************/
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template<bool use_end> void fetch_tms_refresh(int start, int end) {
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#define refresh(location) \
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slot(location): \
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external_slot(location+1);
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#define refreshes_2(location) \
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refresh(location); \
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refresh(location+2);
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#define refreshes_4(location) \
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refreshes_2(location); \
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refreshes_2(location+4);
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#define refreshes_8(location) \
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refreshes_4(location); \
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refreshes_4(location+8);
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switch(start) {
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default: assert(false);
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/* 44 external slots */
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external_slots_32(0)
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external_slots_8(32)
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external_slots_4(40)
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/* 64 refresh/external slot pairs (= 128 windows) */
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refreshes_8(44);
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refreshes_8(60);
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refreshes_8(76);
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refreshes_8(92);
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refreshes_8(108);
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refreshes_8(124);
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refreshes_8(140);
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refreshes_8(156);
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return;
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}
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#undef refreshes_8
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#undef refreshes_4
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#undef refreshes_2
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#undef refresh
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}
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template<bool use_end> void fetch_tms_text(int start, int end) {
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#define fetch_tile_name(location, column) slot(location): line_buffer.names[column].offset = ram_[row_base + column];
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#define fetch_tile_pattern(location, column) slot(location): line_buffer.patterns[column][0] = ram_[row_offset + size_t(line_buffer.names[column].offset << 3)];
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#define fetch_column(location, column) \
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fetch_tile_name(location, column); \
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|
external_slot(location+1); \
|
|
fetch_tile_pattern(location+2, column);
|
|
|
|
#define fetch_columns_2(location, column) \
|
|
fetch_column(location, column); \
|
|
fetch_column(location+3, column+1);
|
|
|
|
#define fetch_columns_4(location, column) \
|
|
fetch_columns_2(location, column); \
|
|
fetch_columns_2(location+6, column+2);
|
|
|
|
#define fetch_columns_8(location, column) \
|
|
fetch_columns_4(location, column); \
|
|
fetch_columns_4(location+12, column+4);
|
|
|
|
LineBuffer &line_buffer = line_buffers_[write_pointer_.row];
|
|
const size_t row_base = pattern_name_address_ & (0x3c00 | size_t(write_pointer_.row >> 3) * 40);
|
|
const size_t row_offset = pattern_generator_table_address_ & (0x3800 | (write_pointer_.row & 7));
|
|
|
|
switch(start) {
|
|
default: assert(false);
|
|
|
|
/* 47 external slots (= 47 windows) */
|
|
external_slots_32(0)
|
|
external_slots_8(32)
|
|
external_slots_4(40)
|
|
external_slots_2(44)
|
|
external_slot(46)
|
|
|
|
/* 40 column fetches (= 120 windows) */
|
|
fetch_columns_8(47, 0);
|
|
fetch_columns_8(71, 8);
|
|
fetch_columns_8(95, 16);
|
|
fetch_columns_8(119, 24);
|
|
fetch_columns_8(143, 32);
|
|
|
|
/* 5 more external slots */
|
|
external_slots_4(167);
|
|
external_slot(171);
|
|
|
|
return;
|
|
}
|
|
|
|
#undef fetch_columns_8
|
|
#undef fetch_columns_4
|
|
#undef fetch_columns_2
|
|
#undef fetch_column
|
|
#undef fetch_tile_pattern
|
|
#undef fetch_tile_name
|
|
}
|
|
|
|
template<bool use_end> void fetch_tms_character(int start, int end) {
|
|
#define sprite_fetch_coordinates(location, sprite) \
|
|
slot(location): \
|
|
slot(location+1): \
|
|
line_buffer.active_sprites[sprite].x = \
|
|
ram_[\
|
|
sprite_attribute_table_address_ & size_t(0x3f81 | (line_buffer.active_sprites[sprite].index << 2))\
|
|
];
|
|
|
|
// This implementation doesn't refetch Y; it's unclear to me
|
|
// whether it's refetched.
|
|
|
|
#define sprite_fetch_graphics(location, sprite) \
|
|
slot(location): \
|
|
slot(location+1): \
|
|
slot(location+2): \
|
|
slot(location+3): {\
|
|
const uint8_t name = ram_[\
|
|
sprite_attribute_table_address_ & size_t(0x3f82 | (line_buffer.active_sprites[sprite].index << 2))\
|
|
] & (sprites_16x16_ ? ~3 : ~0);\
|
|
line_buffer.active_sprites[sprite].image[2] = ram_[\
|
|
sprite_attribute_table_address_ & size_t(0x3f83 | (line_buffer.active_sprites[sprite].index << 2))\
|
|
];\
|
|
line_buffer.active_sprites[sprite].x -= (line_buffer.active_sprites[sprite].image[2] & 0x80) >> 2;\
|
|
const size_t graphic_location = sprite_generator_table_address_ & size_t(0x3800 | (name << 3) | line_buffer.active_sprites[sprite].row); \
|
|
line_buffer.active_sprites[sprite].image[0] = ram_[graphic_location];\
|
|
line_buffer.active_sprites[sprite].image[1] = ram_[graphic_location+16];\
|
|
}
|
|
|
|
#define sprite_fetch_block(location, sprite) \
|
|
sprite_fetch_coordinates(location, sprite) \
|
|
sprite_fetch_graphics(location+2, sprite)
|
|
|
|
#define sprite_y_read(location, sprite) \
|
|
slot(location): posit_sprite(sprite_selection_buffer, sprite, ram_[sprite_attribute_table_address_ & (((sprite) << 2) | 0x3f80)], write_pointer_.row);
|
|
|
|
#define fetch_tile_name(column) line_buffer.names[column].offset = ram_[(row_base + column) & 0x3fff];
|
|
|
|
#define fetch_tile(column) {\
|
|
line_buffer.patterns[column][1] = ram_[(colour_base + size_t((line_buffer.names[column].offset << 3) >> colour_name_shift)) & 0x3fff]; \
|
|
line_buffer.patterns[column][0] = ram_[(pattern_base + size_t(line_buffer.names[column].offset << 3)) & 0x3fff]; \
|
|
}
|
|
|
|
#define background_fetch_block(location, column, sprite) \
|
|
slot(location): fetch_tile_name(column) \
|
|
external_slot(location+1); \
|
|
slot(location+2): \
|
|
slot(location+3): fetch_tile(column) \
|
|
slot(location+4): fetch_tile_name(column+1) \
|
|
sprite_y_read(location+5, sprite); \
|
|
slot(location+6): \
|
|
slot(location+7): fetch_tile(column+1) \
|
|
slot(location+8): fetch_tile_name(column+2) \
|
|
sprite_y_read(location+9, sprite+1); \
|
|
slot(location+10): \
|
|
slot(location+11): fetch_tile(column+2) \
|
|
slot(location+12): fetch_tile_name(column+3) \
|
|
sprite_y_read(location+13, sprite+2); \
|
|
slot(location+14): \
|
|
slot(location+15): fetch_tile(column+3)
|
|
|
|
LineBuffer &line_buffer = line_buffers_[write_pointer_.row];
|
|
LineBuffer &sprite_selection_buffer = line_buffers_[(write_pointer_.row + 1) % mode_timing_.total_lines];
|
|
const size_t row_base = pattern_name_address_ & (size_t((write_pointer_.row << 2)&~31) | 0x3c00);
|
|
|
|
size_t pattern_base = pattern_generator_table_address_;
|
|
size_t colour_base = colour_table_address_;
|
|
int colour_name_shift = 6;
|
|
|
|
if(screen_mode_ == ScreenMode::Graphics) {
|
|
// If this is high resolution mode, allow the row number to affect the pattern and colour addresses.
|
|
pattern_base &= size_t(0x2000 | ((write_pointer_.row & 0xc0) << 5));
|
|
colour_base &= size_t(0x2000 | ((write_pointer_.row & 0xc0) << 5));
|
|
|
|
colour_base += size_t(write_pointer_.row & 7);
|
|
colour_name_shift = 0;
|
|
} else {
|
|
colour_base &= size_t(0xffc0);
|
|
pattern_base &= size_t(0x3800);
|
|
}
|
|
|
|
if(screen_mode_ == ScreenMode::MultiColour) {
|
|
pattern_base += size_t((write_pointer_.row >> 2) & 7);
|
|
} else {
|
|
pattern_base += size_t(write_pointer_.row & 7);
|
|
}
|
|
|
|
switch(start) {
|
|
default: assert(false);
|
|
|
|
external_slots_2(0);
|
|
|
|
sprite_fetch_block(2, 0);
|
|
sprite_fetch_block(8, 1);
|
|
sprite_fetch_coordinates(14, 2);
|
|
|
|
external_slots_4(16);
|
|
external_slot(20);
|
|
|
|
sprite_fetch_graphics(21, 2);
|
|
sprite_fetch_block(25, 3);
|
|
|
|
slot(31):
|
|
sprite_selection_buffer.reset_sprite_collection();
|
|
do_external_slot(31*2);
|
|
external_slots_2(32);
|
|
external_slot(34);
|
|
|
|
sprite_y_read(35, 0);
|
|
sprite_y_read(36, 1);
|
|
sprite_y_read(37, 2);
|
|
sprite_y_read(38, 3);
|
|
sprite_y_read(39, 4);
|
|
sprite_y_read(40, 5);
|
|
sprite_y_read(41, 6);
|
|
sprite_y_read(42, 7);
|
|
|
|
background_fetch_block(43, 0, 8);
|
|
background_fetch_block(59, 4, 11);
|
|
background_fetch_block(75, 8, 14);
|
|
background_fetch_block(91, 12, 17);
|
|
background_fetch_block(107, 16, 20);
|
|
background_fetch_block(123, 20, 23);
|
|
background_fetch_block(139, 24, 26);
|
|
background_fetch_block(155, 28, 29);
|
|
|
|
return;
|
|
}
|
|
|
|
#undef background_fetch_block
|
|
#undef fetch_tile
|
|
#undef fetch_tile_name
|
|
#undef sprite_y_read
|
|
#undef sprite_fetch_block
|
|
#undef sprite_fetch_graphics
|
|
#undef sprite_fetch_coordinates
|
|
}
|
|
|
|
|
|
/***********************************************
|
|
Master System Fetching Code
|
|
************************************************/
|
|
|
|
template<bool use_end> void fetch_sms(int start, int end) {
|
|
#define sprite_fetch(sprite) {\
|
|
line_buffer.active_sprites[sprite].x = \
|
|
ram_[\
|
|
master_system_.sprite_attribute_table_address & size_t(0x3f80 | (line_buffer.active_sprites[sprite].index << 1))\
|
|
] - (master_system_.shift_sprites_8px_left ? 8 : 0); \
|
|
const uint8_t name = ram_[\
|
|
master_system_.sprite_attribute_table_address & size_t(0x3f81 | (line_buffer.active_sprites[sprite].index << 1))\
|
|
] & (sprites_16x16_ ? ~1 : ~0);\
|
|
const size_t graphic_location = master_system_.sprite_generator_table_address & size_t(0x2000 | (name << 5) | (line_buffer.active_sprites[sprite].row << 2)); \
|
|
line_buffer.active_sprites[sprite].image[0] = ram_[graphic_location]; \
|
|
line_buffer.active_sprites[sprite].image[1] = ram_[graphic_location+1]; \
|
|
line_buffer.active_sprites[sprite].image[2] = ram_[graphic_location+2]; \
|
|
line_buffer.active_sprites[sprite].image[3] = ram_[graphic_location+3]; \
|
|
}
|
|
|
|
#define sprite_fetch_block(location, sprite) \
|
|
slot(location): \
|
|
slot(location+1): \
|
|
slot(location+2): \
|
|
slot(location+3): \
|
|
slot(location+4): \
|
|
slot(location+5): \
|
|
sprite_fetch(sprite);\
|
|
sprite_fetch(sprite+1);
|
|
|
|
#define sprite_y_read(location, sprite) \
|
|
slot(location): \
|
|
posit_sprite(sprite_selection_buffer, sprite, ram_[master_system_.sprite_attribute_table_address & ((sprite) | 0x3f00)], write_pointer_.row); \
|
|
posit_sprite(sprite_selection_buffer, sprite+1, ram_[master_system_.sprite_attribute_table_address & ((sprite + 1) | 0x3f00)], write_pointer_.row); \
|
|
|
|
#define fetch_tile_name(column, row_info) {\
|
|
const size_t scrolled_column = (column - horizontal_offset) & 0x1f;\
|
|
const size_t address = row_info.pattern_address_base + (scrolled_column << 1); \
|
|
line_buffer.names[column].flags = ram_[address+1]; \
|
|
line_buffer.names[column].offset = size_t( \
|
|
(((line_buffer.names[column].flags&1) << 8) | ram_[address]) << 5 \
|
|
) + row_info.sub_row[(line_buffer.names[column].flags&4) >> 2]; \
|
|
}
|
|
|
|
#define fetch_tile(column) \
|
|
line_buffer.patterns[column][0] = ram_[line_buffer.names[column].offset]; \
|
|
line_buffer.patterns[column][1] = ram_[line_buffer.names[column].offset+1]; \
|
|
line_buffer.patterns[column][2] = ram_[line_buffer.names[column].offset+2]; \
|
|
line_buffer.patterns[column][3] = ram_[line_buffer.names[column].offset+3];
|
|
|
|
#define background_fetch_block(location, column, sprite, row_info) \
|
|
slot(location): fetch_tile_name(column, row_info) \
|
|
external_slot(location+1); \
|
|
slot(location+2): \
|
|
slot(location+3): \
|
|
slot(location+4): \
|
|
fetch_tile(column) \
|
|
fetch_tile_name(column+1, row_info) \
|
|
sprite_y_read(location+5, sprite); \
|
|
slot(location+6): \
|
|
slot(location+7): \
|
|
slot(location+8): \
|
|
fetch_tile(column+1) \
|
|
fetch_tile_name(column+2, row_info) \
|
|
sprite_y_read(location+9, sprite+2); \
|
|
slot(location+10): \
|
|
slot(location+11): \
|
|
slot(location+12): \
|
|
fetch_tile(column+2) \
|
|
fetch_tile_name(column+3, row_info) \
|
|
sprite_y_read(location+13, sprite+4); \
|
|
slot(location+14): \
|
|
slot(location+15): fetch_tile(column+3)
|
|
|
|
// Determine the coarse horizontal scrolling offset; this isn't applied on the first two lines if the programmer has requested it.
|
|
LineBuffer &line_buffer = line_buffers_[write_pointer_.row];
|
|
LineBuffer &sprite_selection_buffer = line_buffers_[(write_pointer_.row + 1) % mode_timing_.total_lines];
|
|
const int horizontal_offset = (write_pointer_.row >= 16 || !master_system_.horizontal_scroll_lock) ? (line_buffer.latched_horizontal_scroll >> 3) : 0;
|
|
|
|
// Limit address bits in use if this is a SMS2 mode.
|
|
const bool is_tall_mode = mode_timing_.pixel_lines != 192;
|
|
const size_t pattern_name_address = master_system_.pattern_name_address | (is_tall_mode ? 0x800 : 0);
|
|
const size_t pattern_name_offset = is_tall_mode ? 0x100 : 0;
|
|
|
|
// Determine row info for the screen both (i) if vertical scrolling is applied; and (ii) if it isn't.
|
|
// The programmer can opt out of applying vertical scrolling to the right-hand portion of the display.
|
|
const int scrolled_row = (write_pointer_.row + master_system_.latched_vertical_scroll) % (is_tall_mode ? 256 : 224);
|
|
struct RowInfo {
|
|
size_t pattern_address_base;
|
|
size_t sub_row[2];
|
|
};
|
|
const RowInfo scrolled_row_info = {
|
|
(pattern_name_address & size_t(((scrolled_row & ~7) << 3) | 0x3800)) - pattern_name_offset,
|
|
{size_t((scrolled_row & 7) << 2), 28 ^ size_t((scrolled_row & 7) << 2)}
|
|
};
|
|
RowInfo row_info;
|
|
if(master_system_.vertical_scroll_lock) {
|
|
row_info.pattern_address_base = (pattern_name_address & size_t(((write_pointer_.row & ~7) << 3) | 0x3800)) - pattern_name_offset;
|
|
row_info.sub_row[0] = size_t((write_pointer_.row & 7) << 2);
|
|
row_info.sub_row[1] = 28 ^ size_t((write_pointer_.row & 7) << 2);
|
|
} else row_info = scrolled_row_info;
|
|
|
|
// ... and do the actual fetching, which follows this routine:
|
|
switch(start) {
|
|
default: assert(false);
|
|
|
|
sprite_fetch_block(0, 0);
|
|
sprite_fetch_block(6, 2);
|
|
|
|
external_slots_4(12);
|
|
external_slot(16);
|
|
|
|
sprite_fetch_block(17, 4);
|
|
sprite_fetch_block(23, 6);
|
|
|
|
slot(29):
|
|
sprite_selection_buffer.reset_sprite_collection();
|
|
do_external_slot(29*2);
|
|
external_slot(30);
|
|
|
|
sprite_y_read(31, 0);
|
|
sprite_y_read(32, 2);
|
|
sprite_y_read(33, 4);
|
|
sprite_y_read(34, 6);
|
|
sprite_y_read(35, 8);
|
|
sprite_y_read(36, 10);
|
|
sprite_y_read(37, 12);
|
|
sprite_y_read(38, 14);
|
|
|
|
background_fetch_block(39, 0, 16, scrolled_row_info);
|
|
background_fetch_block(55, 4, 22, scrolled_row_info);
|
|
background_fetch_block(71, 8, 28, scrolled_row_info);
|
|
background_fetch_block(87, 12, 34, scrolled_row_info);
|
|
background_fetch_block(103, 16, 40, scrolled_row_info);
|
|
background_fetch_block(119, 20, 46, scrolled_row_info);
|
|
background_fetch_block(135, 24, 52, row_info);
|
|
background_fetch_block(151, 28, 58, row_info);
|
|
|
|
external_slots_4(167);
|
|
|
|
return;
|
|
}
|
|
|
|
#undef background_fetch_block
|
|
#undef fetch_tile
|
|
#undef fetch_tile_name
|
|
#undef sprite_y_read
|
|
#undef sprite_fetch_block
|
|
#undef sprite_fetch
|
|
}
|
|
|
|
#undef external_slot
|
|
#undef slot
|
|
|
|
uint32_t *pixel_target_ = nullptr, *pixel_origin_ = nullptr;
|
|
bool asked_for_write_area_ = false;
|
|
void draw_tms_character(int start, int end);
|
|
void draw_tms_text(int start, int end);
|
|
void draw_sms(int start, int end, uint32_t cram_dot);
|
|
};
|
|
|
|
}
|
|
}
|
|
|
|
#endif /* TMS9918Base_hpp */
|