CLK/Components at 2017-01-30 - CLK - Applefritter: Git

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Thomas Harte ced644b103 It seems likely that an AY divides its clock by 8, not 16. I had conflated wave frequency and counter clock.

2017-01-11 22:03:01 -05:00

..

Added a CRC check for read address, ensured CRC, lost data and record not found are initially reset.

2017-01-01 21:00:25 -05:00

Converted all 'Components' to postfix underscores.

2016-12-03 10:51:09 -05:00

Converted all 'Components' to postfix underscores.

2016-12-03 10:51:09 -05:00

Restored Vic audio.

2016-12-03 17:10:47 -05:00

It seems likely that an AY divides its clock by 8, not 16. I had conflated wave frequency and counter clock.

2017-01-11 22:03:01 -05:00