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Minor text improvements. No fix yet as to fast RAM refresh rate.

Thomas Harte 2020-11-09 15:48:42 -05:00
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Apple-IIgs-Memory-Map.md

@ -8,11 +8,11 @@ ROM access is always 'fast' — access windows are five cycles of the 14Mhz cloc
# Banks $E0 and $E1: Mega II RAM, card access
Banks $E0 and $E1 access memory via the IIe-emulating Mega II chip. Bank $E0 contains main RAM and bank $E1 contains auxiliary RAM and are subject to language-card banking only. The video buffer always natively lives in this area.
Banks $E0 and $E1 access memory via the IIe-emulating Mega II chip. Bank $E0 contains main RAM and bank $E1 contains auxiliary RAM. They are subject to language-card banking only. The video buffer always natively lives in this area.
Both reads and writes are performed via the Mega II so are 'slow' — access windows are usually fourteen cycles of the 14Mhz clock though every 64th is stretched to sixteen cycles as per the original hardware to ensure that IIe-style video remains in phase with the colour subcarrier.
Both reads and writes are performed via the Mega II so are 'slow' — access windows are usually fourteen cycles of the 14Mhz clock though every 64th is stretched to sixteen cycles as per the original hardware to ensure that IIe-style video remains in phase with the NTSC colour subcarrier.
# Banks $00–$7f: Fast RAM
# Banks $02–$7f: Fast RAM
Banks $02–$7f contain regular system RAM and are not subject to paging or other rearrangement.
@ -24,6 +24,6 @@ The first 128kb of fast RAM occupies banks $00 and $01.
Language card banking affects both pages; other auxiliary/main selections may expose parts of bank $01 within bank $00. Regardless of language card setting, the 65816's VPB (i.e. vector pull) signal selects ROM rather than RAM.
Parts of the pages may additionally be shadowed up to corresponding regions of $e0 and $e1, i.e. to act as a write-through cache, depending on the register at $c035.
Parts of the pages may additionally be shadowed up to corresponding regions of $e0 and $e1, i.e. to act as a write-through cache, depending on the register at $c035. Auxiliary paging is applied before shadowing so a write to bank $00 that ends up being redirected to $01 will be shadowed to $e1 if shadowing is enabled.
The speed register at $c036 also has a bank shadowing control bit; if bit 4 is set to 1 then shadowing will apply in all banks. Otherwise it will apply in $01 and $02 only.
The speed register at $c036 also has a bank shadowing control bit; if bit 4 is set to 1 then shadowing will apply in all banks, based only upon the lowest address line. Otherwise it will apply in banks $01 and $02 only.