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Added ZX81 text.

Thomas Harte 2017-06-14 14:46:03 -04:00
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The-ZX80-and-ZX81.md

@ -40,3 +40,27 @@ As designed, lines of text are assembled in memory, terminated by a HALT instruc
Unintentionally, the refresh counter can be used as a direct video address with compatible RAM. Unintentionally, the refresh counter can be used as a direct video address with compatible RAM.
It's also possible to reset the line counter repeatedly by triggering programmatic sync at the same time as the automatic sync would occur anyway, as the two things are ORd. It's also possible to reset the line counter repeatedly by triggering programmatic sync at the same time as the automatic sync would occur anyway, as the two things are ORd.
The ROM is written such that the total number of cycles per line is 207.
# Video Generation on the ZX81
The ZX81 adds an additional 207-cycle counter, along with NMI and WAIT logic; it slightly adjusts horizontal sync timing.
Interrupt acknowledge now resets the 207-cycle counter. [Horizontal] sync is signalled when that counter reaches 16 and until it reaches 32. The counter automatically resets itself upon reaching 207.
NMI generation is optional. It is enabled by outputting to any port with the lowest address line clear. It is disabled by outputting to any port with bit 1 of the address line clear.
When NMI generation is enabled, the NMI line will be asserted at the same time as horizontal sync is generated.
If the HALT output of the Z80 is not active and the NMI line is active then the WAIT line will also be held active.
## Net Effect
Because the 207-cycle counter is capable of triggering a regular horizontal sync without any additional intervention, the ZX81 no longer needs to cycle count during blank lines. It can be doing other work mostly without any regard to the display.
NMI generation allows the Z80 to count lines so that it knows where the display is vertically, and therefore when to resume active painting.
WAIT generation provides a means of horizontal resynchronisation between the processor and the raster beam.
Additional discussion: Wilf Rigter has observed that WAIT logic would work equally well for synchronisation if applied only when HALT **is** active, and would free up around 10% of additional processing time for non-display processing; he speculates that Sinclair implemented it this way around for a slight cost reduction.