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Minor copy fixes; no new substance.
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@ -3,11 +3,11 @@ The Mockingboards are a series of audio expansions for the Apple II, the most co
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## AY-3-8910s
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Each AY is connected to its 6522:
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* the 6522 port A connected to the AY's data pins;
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* bit 0 of the 6522's port B connected to the AY's BC1;
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* bit 1 of the 6522's port B connected to the AY's BCDIR;
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* BC2 connected to +5v; and
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* bit 2 of the 6522's port B connected to the AY's reset.
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* port A is connected to the AY's data pins;
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* bit 0 of port B is connected to the AY's BC1;
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* bit 1 of port B is connected to the AY's BCDIR;
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* BC2 is connected to +5v; and
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* bit 2 of port B is connected to the AY's reset.
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The three channels from each AY are mixed together with equal volume.
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@ -15,7 +15,7 @@ The three channels from each AY are mixed together with equal volume.
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The 6522s are exposed to the processor's bus:
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* the four register select lines are connected to address lines 0 to 3; and
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* the reset and data lines connected as expected.
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* the reset and data lines connect as expected.
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The 6522 for the left channel:
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* is selected when address line 7 is low; and
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@ -27,16 +27,15 @@ The 6522 for the right channel:
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Both also require the board's IOSEL to be active — they appear only in the ordinary IO area for their board.
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## SSI-263s
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The SSI-263s are more directly connected to the processor's bus.
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Both SSIs:
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* are connected directly to the processor's data bus;
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* have their three register select lines connected to the low three bits of the address bus;
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* connect their data bus directly to the processor's data bus;
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* connect their three register select lines to the low three bits of the address bus;
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* use IOSELECT as a prerequisite for chip selection; and
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* have their A/R output (i.e. the signal that "may be used as an interrupt request for new phoneme data") connected to the corresponding 6522's CA1.
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* connect their A/R output (i.e. the signal that "may be used as an interrupt request for new phoneme data") to the corresponding 6522's CA1.
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The left channel SSI-263:
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* is selected when A5 is high.
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@ -46,4 +45,4 @@ The right channel SSI-263:
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## Clock Rate
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All chips are clocked according to the Apple card's phase 1 clock input. So they are clocked at the same rate as the CPU.
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All chips are clocked according to the Apple card's phase 1 clock input. So they are clocked at the same rate as the CPU.
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