6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-02-16 03:31:41 +00:00
Code Issues Projects Releases Wiki Activity

Corrected statement of ZX81 slow video generation and Wilf's adjustment thereto.

Thomas Harte 2017-06-22 21:39:41 -04:00
parent 466e08eb34
commit bf07e6293a
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
The-ZX80-and-ZX81.md

@ -63,6 +63,6 @@ Because the 207-cycle counter is capable of triggering a regular horizontal sync
NMI generation allows the Z80 to count lines so that it knows where the display is vertically, and therefore when to resume active painting.
WAIT generation provides a means of horizontal resynchronisation between the processor and the raster beam.
WAIT generation provides a means of horizontal resynchronisation between the processor and the raster beam — intended use is that the ROM hits a HALT and sits there. An NMI is triggered. The CPU exits the halt state. At that point WAIT is asserted. The CPU gets through the second cycle of its NMI sequence, to where it will next honour a wait request, and starts performing wait cycles. Eventually the ULA stops asserting NMI. So it also stops asserting WAIT. The NMI is then permitted to finish its sequence and nine cycles after the end of horizontal sync, execution begins at 0x66.
Additional discussion: Wilf Rigter has observed that WAIT logic would work equally well for synchronisation if applied only when HALT **is** active, and would free up around 10% of additional processing time for non-display processing; he speculates that Sinclair implemented it this way around for a slight cost reduction.
Additional discussion: Wilf Rigter has observed that WAIT logic would work equally well for synchronisation if applied only if it detects a transition of HALT from active to inactive, which would free up around 10% of additional processing time for non-display processing because the NMI + not HALT condition also applies when the CPU isn't trying to synchronise at all; he speculates that Sinclair declined to do so for a slight cost reduction.